Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Interposer with identification system
US10290606B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10290606-B2 |
| Application number | US-201213529736-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 21, 2012 |
| Priority date | Jun 21, 2012 |
| Publication date | May 14, 2019 |
| Grant date | May 14, 2019 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing, comprising: coupling an identification structure to an interposer, the identification structure being operable to provide an output that identifies the interposer; and wherein the identification structure includes a multi-bit data system and is programmable to create or alter the output and the output can include bits with a combination of both logic 1 and logic 0 values. 2. The method of claim 1 , wherein the coupling comprises forming the identification structure and whereby the formed identification structure forms part of the interposer. 3. The method of claim 1 , wherein the coupling comprises attaching the identification structure to the interposer. 4. The method of claim 1 , wherein the identification structure comprises a fuse, a component mounted on the interposer or a wireless transmission device. 5. The method of claim 4 , wherein the identification structure comprises a conductor strap on or in the interposer. 6. The method of claim 1 , comprising mounting a semiconductor chip on the interposer. 7. The method of claim 6 , wherein the semiconductor chip is operable to read the output. 8. The method of claim 1 , comprising mounting the interposer on a substrate. 9. The method of claim 1 , comprising electrically connecting an electronic device to the interposer, the electronic device being operable to read the output. 10. A method of manufacturing, comprising: engaging an interposer having an identification structure operable to provide an output that identifies the interposer, the identification structure including a multi-bit data system and the output can include bits with a combination of both logic 1 and logic 0 values; and programming the identification structure to create or alter the output. 11. The method of claim 10 , wherein the identification structure comprises a fuse, a component mounted on the interposer or a wireless transmission device. 12. The method of claim 11 , wherein the identification structure comprises a conductor strap on or in the interposer. 13. The method of claim 10 , comprising mounting a semiconductor chip on the interposer. 14. The method of claim 13 , comprising reading the output with the semiconductor chip. 15. The method of claim 10 , comprising mounting the interposer on a substrate. 16. The method of claim 10 , comprising electrically connecting an electronic device to the interposer and using the electronic device to read the output. 17. The method of claim 10 , comprising programming the output based on a process step performed on the interposer. 18. The method of claim 17 , comprising performing the process step on the interposer. 19. The method of claim 10 , comprising sorting the interposer based on the output.
Assignees
Inventors
Classifications
characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title
batch processes · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between stacked chips · CPC title
Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10290606B2 cover?
- Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.
- Who is the assignee on this patent?
- Alfano Michael, Siegel Joe, Su Michael Z, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 14 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).