Cooler with emi-limiting inductor

Patent metadata

Field	Value
Publication number	US-10290587-B2
Application number	US-201715622802-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Nov 3, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.

First claim

The invention claimed is:

1. A power device package, comprising:
a dielectric substrate including an upper conductor layer and a lower conductor layer;
a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive;
a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate attached to the top surface of the protruding hillock via an adhesive; and
magnetic material coupled to the protruding hillock, the magnetic material includes inner sides abutting the outer sides of the protruding hillock.

2. The power device package of claim 1 , wherein the magnetic material includes a hole adapted to mate with the protruding hillock.

3. The power device package of claim 1 , further comprising a second protruding hillock coupled to the magnetic material.

4. The power device package of claim 1 , wherein the cooler is a heat sink.

5. The power device package of claim 1 , wherein the semiconductor die is a silicon carbide die.

6. The power device package of claim 1 , wherein the magnetic material and the protruding hillock form an inductor with inductance exceeding 11 microHenry.

7. A power device assembly, comprising:
a chassis,
a first and a second power device package, wherein the first and second power device package each include:
a plurality of semiconductor dies, wherein each die of the plurality of semiconductor dies includes at least one transistor,
a dielectric substrate that provides electrical connections to the plurality of semiconductor dies via a patterned conductor layer, the dielectric substrate includes a lower conductor layer insulated from the patterned conductor layer,
a cooler that includes a plurality of hillocks each including a top surface and perimeter surfaces, at least a portion of the top surfaces of the plurality of hillocks being attached to the lower conductor layer via adhesive, and
damping means for reducing electromagnetic interference current, wherein the damping means abut the perimeter surfaces of the plurality of hillocks; and

interconnect wires that provide electrical connections between the first and second power device package.

8. The power device assembly of claim 7 , wherein the cooler is a heat spreader.

9. The power device assembly of claim 7 , further comprising silicon carbide metal-oxide-semiconductor field-effect transistors on the plurality of semiconductor dies.

10. The power device assembly of claim 7 , wherein the damping means includes a magnetic frame that couples mateably around the plurality of hillocks.

11. The power device assembly of claim 10 , wherein the magnetic frame includes two or more sub-frames.

12. The power device assembly of claim 10 , wherein the magnetic frame includes soft magnetic material selected from a group consisting of Iron Oxide, Zinc, Manganese, and Nickel.

13. The power device assembly of claim 10 , wherein the magnetic frame includes magnetic material that increases a cooler inductance of the cooler.

14. The power circuit of claim 7 , wherein first and second driving transistors are disposed on at least two semiconductor substrates.

15. A method of operating a power device, comprising:
activating a DC voltage supply;
providing a current to a plurality of semiconductor dies; and
damping an electromagnetic interference current by:
providing a magnetic material abutting hillocks of a cooler, the magnetic material amplifying inductance values of the hillocks of the cooler,
grounding the cooler by connecting the cooler to a ground terminal, and
providing a conduction path for the electromagnetic interference current through the cooler;

wherein the damping of the electromagnetic interference current reduces an amount of electrical charge flowing into the ground terminal during the activation of the DC voltage supply.

16. The method of claim 15 , further comprising the steps of:
deactivating the DC voltage supply; and
damping a second electromagnetic interference current, wherein the damping of the second electromagnetic interference current reduces a second amount of electrical charge flowing out of the ground terminal during the deactivation of the DC voltage supply.

17. The method of claim 15 , further comprising the step of dissipating heat generated by the plurality of semiconductor dies via the cooler.

18. The method of claim 15 , further comprising the step of switching one or more silicon carbide transistors on the plurality of semiconductor dies.

19. The method of claim 18 , further comprising the step of driving a drain current greater than 100 A through the one or more silicon carbide transistors.

20. The circuit of claim 18 , further comprising the step of applying a drain-to-source voltage greater than 1000 V to the one or more silicon carbide transistors.

Assignees

• Toyota Eng & Mfg North America
• Virginia Tech Intellectual Properties Inc

Inventors

• Ngo Khai
• Wang Chi-Ming
• Cui Han

Classifications

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title