Semiconductor device

Patent metadata

Field	Value
Publication number	US-10290583-B2
Application number	US-201715467051-A
Country	US
Kind code	B2
Filing date	Mar 23, 2017
Priority date	Mar 24, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An object of the present invention is to shorten the switching delay time of a semiconductor device.
Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a source bus line and a drain bus line that are provided apart from each other over a main surface of a substrate in a first direction in planar view;
a transistor unit that is provided between the source bus line and the drain bus line;
a plurality of gate electrodes that extends in the first direction in the transistor unit and is provided apart from each other in a second direction orthogonal to the first direction in planar view;
a gate bus line that is electrically coupled to the gate electrodes, wherein the gate electrodes are formed in a first wiring layer, wherein the source bus line and the drain bus line are formed in a second wiring layer above the first wiring layer, and wherein the gate bus line is formed in a third wiring layer above the second wiring layer;
a plurality of source electrodes that is formed in the second wiring layer in the transistor unit and is provided apart from each other in the second direction while extending in the first direction;
a plurality of drain electrodes that is formed in the second wiring layer in the transistor unit and is provided apart from each other in the second direction while extending in the first direction; and
a gate connection line that is formed in the first wiring layer and extends in the second direction, wherein
the source electrodes and the drain electrodes are alternately provided in the second direction,
the gate electrode is arranged between a part where the source electrode is coupled to the substrate and a part where the drain electrode is coupled to the substrate,
one ends of the source electrodes in the first direction are coupled by the source bus line,
one ends of the drain electrodes in the first direction are coupled by the drain bus line,
one ends of the gate electrodes in the first direction are coupled by the gate connection line,
the gate bus line is located above the gate connection line,
a part of the source electrode is located between the gate connection line and the gate bus line, and
the gate connection line and the gate bus line are electrically coupled to each other through a connection part penetrating the source electrode.

2. The semiconductor device according to claim 1 ,
wherein the connection part includes:
an interlayer insulating film formed between the gate connection line and the gate bus line;
a connection hole penetrating the interlayer insulating film; and
a plug electrode embedded into the connection hole.

3. The semiconductor device according to claim 1 ,
wherein the connection part includes a pad electrode configured using the second wiring layer between the gate connection line and the gate bus line, and
wherein the gate connection line and the gate bus line are electrically coupled to each other through the pad electrode.

4. The semiconductor device according to claim 1 ,
wherein the gate connection line and the gate bus line are electrically coupled to each other through a connection part provided between the gate connection line and the gate bus line at a region where the source electrodes and the drain electrodes are not formed.

5. The semiconductor device according to claim 4 ,
wherein the connection part includes:
an interlayer insulating film formed between the gate connection line and the gate bus line;
a connection hole penetrating the interlayer insulating film; and
a plug electrode embedded into the connection hole.

6. The semiconductor device according to claim 4 ,
wherein the connection part includes a pad electrode configured using the second wiring layer between the gate connection line and the gate bus line, and
wherein the gate connection line and the gate bus line are electrically coupled to each other through the pad electrode.

7. The semiconductor device according to claim 1 ,
wherein a width of the gate bus line in the first direction is larger than that of the gate connection line in the first direction.

8. The semiconductor device according to claim 1 ,
wherein one ends of the gate electrodes in the first direction located on both sides of the source electrode in the second direction are coupled by the gate connection line.

9. The semiconductor device according to claim 1 ,
wherein one ends of the gate electrodes in the first direction located on both sides of the drain electrode in the second direction are coupled by the gate connection line.

10. The semiconductor device according to claim 9 ,
wherein the gate connection line and the gate bus line are electrically coupled to each other through a connection part provided between the gate connection line and the gate bus line, and
wherein the connection part includes:
an interlayer insulating film formed between the gate connection line and the gate bus line;
a connection hole penetrating the interlayer insulating film; and
a plug electrode embedded into the connection hole.

11. The semiconductor device according to claim 9 ,
wherein the gate connection line and the gate bus line are electrically coupled to each other through a connection part provided between the gate connection line and the gate bus line,
wherein the connection part includes a pad electrode configured using the second wiring layer between the gate connection line and the gate bus line, and
wherein the gate connection line and the gate bus line are electrically coupled to each other through the pad electrode.

12. The semiconductor device according to claim 1 ,
wherein the gate bus line is not overlapped with the source bus line and the drain bus line in planar view.

13. The semiconductor device according to claim 1 ,
wherein the gate bus line is overlapped with a part of the transistor unit in planar view.

14. The semiconductor device according to claim 1 ,
wherein the gate bus line includes:
a first part extending in the first direction; and
a second part extending in the second direction on both sides of the first part, wherein the second part is located above the gate connection line.

15. The semiconductor device according to claim 1 ,
wherein a first wire bonded to the source bus line, a second wire bonded to the drain bus line, and a third wire bonded to the gate bus line are provided.

Assignees

• Renesas Electronics Corp

Inventors

• Miura Yoshinao

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5438

  the bond wires having multiple connections on the same bond pad · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/43

  Layouts of interconnections · CPC title