Integrated superconductor device and method of fabrication

Patent metadata

Field	Value
Publication number	US-10290399-B2
Application number	US-201815906532-A
Country	US
Kind code	B2
Filing date	Feb 27, 2018
Priority date	Nov 12, 2013
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

First claim

What is claimed is:

1. A method to form a superconductor device, comprising:
depositing a crystalline layer having a preferred crystallographic orientation on a substrate formed of glass, the crystalline layer comprising a layer of silicon nitride, a first layer of MgO disposed on the layer of silicon nitride, and a separate, second layer of MgO disposed on the first layer of MgO, the second layer of MgO having a higher degree of crystalline orientation relative to the first layer of MgO;
forming an oriented superconductor layer comprising an oriented superconductor material on the crystalline layer;
depositing a conductive strip having a non-linear pattern; and
treating an exposed portion of the oriented superconductor layer not covered by the conductive strip to transform the exposed portion into a non-superconductor material.

2. The method of claim 1 , wherein the substrate comprises a first side and a second side, wherein the conductive strip is deposited on the first side, the method further comprising:
depositing a second intermediate layer on the substrate base on the second side, the second intermediate layer comprising a preferred crystallographic orientation;
depositing a second oriented superconductor layer on the second intermediate layer;
depositing a second conductive strip on a portion of the second oriented superconductor layer to define a second protected region of the second oriented superconductor layer thereunder, and a second exposed region of the second oriented superconductor layer adjacent the protected region; and
electrically connecting the second conductive strip to the first conductive strip.

3. The method of claim 2 , further comprising providing the first and second conductive strips each as bifilar wound conductive strips.

4. The method of claim 1 , wherein the superconductor layer comprises RBa 2 Cu 3 O 7-x where R is a rare earth element.

5. The method of claim 1 , further comprising providing the conductive strip in a serpentine pattern.

6. The method of claim 1 , further comprising annealing the substrate to form a non-superconductor material in the exposed region.

7. The method of claim 1 , further comprising depositing a protective coating on the conductive strip and exposed region.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Wang Connie P
• Murphy Paul
• Sullivan Paul

Classifications

• H01L39/16

  Electricity · mapped topic

• H01B12/06 Primary

  Films or wires on bases or cores · CPC title

• H01B13/30

  Drying; Impregnating (H01B13/32 takes precedence) · CPC title

• H02H9/023

  Current limitation using superconducting elements · CPC title

• H10N60/30

  Devices switchable between superconducting and normal states · CPC title