Methods and apparatuses including command delay adjustment circuit

Patent metadata

Field	Value
Publication number	US-10290336-B2
Application number	US-201715595056-A
Country	US
Kind code	B2
Filing date	May 15, 2017
Priority date	Apr 26, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

First claim

What is claimed is:

1. An apparatus comprising:
a first circuit configured to respond to a first clock signal to latch a first signal, the first circuit being configured to provide a second signal;
a second circuit coupled to the first circuit to latch the second signal, the second circuit being configured to provide a third signal based on the second signal in response to a first output timing signal that is substantially in phase to the first clock signal; and
a clock input buffer circuit configured to generate the first clock signal in response to an enable signal,
wherein the first circuit is coupled to the clock input buffer circuit and further configured to provide the enable signal to the clock input buffer.

2. The apparatus as claimed in claim 1 , wherein the first circuit is configured to decode the first signal to provide the second signal.

3. The apparatus as claimed in claim 2 , wherein the first circuit is a command decoder circuit and the first signal includes a command signal.

4. The apparatus as claimed in claim 1 , further comprising:
a first delay circuit configured to receive a second clock signal that is substantially in phase to the first clock signal and further configured to provide a third clock signal by delaying the second clock signal by a first delay that is adjustable;
a second delay circuit coupled to the second circuit and configured to provide a fourth signal by delaying the third signal by a second delay that is adjustable; and
a delay control circuit configured to adjust the first delay of the first circuit and the second delay of the second delay circuit to be substantially equal to each other.

5. The apparatus as claimed in claim 4 , further comprising:
a third circuit coupled to the second delay circuit and configured to provide a fifth signal by delaying the fourth signal in response to the third clock signal and latency information; and
an output buffer coupled to the third circuit and configured to be activated in response to the fifth signal and further configured to operate in response to the third clock signal.

6. The apparatus as claimed in claim 1 , wherein the second circuit is further configured to latch the second signal in response to a first input signal that is delayed in phase from the first clock signal.

7. The apparatus as claimed in claim 6 ,
wherein the second circuit further comprises:
a counter circuit configured to receive the first clock signal and further configured to provide a plurality of timing control signals in response to the first clock signal;
a third delay circuit coupled to the counter circuit and configured to provide a plurality of second input timing signals by delaying the timing control signals;
a first decoder coupled to the third delay circuit and configured to provide a first input timing signal by decoding the second input timing signals; and
a second decoder coupled to the counter circuit and configured to provide the first output timing signal by decoding the timing control signals.

8. The apparatus as claimed in claim 7 , wherein the third delay circuit is configured to represent a first delay that is substantially constant.

9. The apparatus as claimed in claim 7 , wherein
the first decoder is further configured to provide a third input timing signal by decoding the second input timing signals,
wherein the second decoder is further configured to provide a second output timing signal by decoding the timing control signals, and
wherein the second circuit further comprises:
first and second input latch circuits coupled in common to the first circuit and configured to latch the second signal in response to the first input timing signal and the second input timing signal, respectively;
first and second output latch circuits coupled to the first and second input latch circuit and configured to output the third signal in response to the first output timing signal and the second output timing signal, respectively; and
a selector circuit including first and second input nodes coupled respectively to the first and second input latch circuits and first and second output nodes coupled respectively to the first and second output latch circuits, the selector circuit being configured to couple the first and second input latch circuits to the first and second output latch circuit in response to a selector control signal.

10. The apparatus as claimed in claim 9 , further comprising:
a third circuit coupled to the second circuit and configured to provide the selector control signal in response to a latency information.

11. A method comprising:
providing a system clock signal;
latching command signals respective to the system clock signal;
providing a signal based on the command signals;
latching the signal responsive to the system clock signal; and
providing a clock-synchronized read signal responsive to latency information,
wherein the latency information used to provide the clock-synchronized read signal is a latency between the system clock signal and the clock-synchronized read signal, and the clock-synchronized read signal is provided based on both the command signals and the signal latched responsive to the system clock signal.

12. The method of claim 11 , wherein the system clock signal is based on an external clock signal.

13. The method of claim 11 , wherein the clock synchronized read signal is responsive to a shift cycle parameter responsive to the latency information.

14. The method of claim 11 , wherein latching command signals responsive to the system clock signal comprises:
latching the command signals responsive a first clock signal responsive to the system clock signal;
providing a read signal or a write signal as an output signal responsive to a read command or a write command on the command signals;
latching the read signal or the write signal responsive to a second clock signal responsive to the first clock signal;
providing the latched read signal or the latched write signal as an internal signal;
latching the internal signal responsive to the second clock signal; and
providing an enable signal responsive to the latched internal signal.

15. The method of claim 14 , wherein the providing the system clock signal comprises:
providing a reference clock signal responsive to the enable signal.

16. The method of claim 15 , wherein providing the system clock signal comprises:
providing the reference clock signal and the system clock signal based on an external clock signal.

17. The method of claim 11 , wherein latching the signal responsive to the system clock signal comprises:
receiving the system clock signal;
providing a plurality of first timing control signals responsive to the system clock signal,
providing a plurality of second timing control signals that has a predetermined delay from the system clock signal; and
providing pointer input signals by decoding the plurality of second timing control signals, and
wherein providing the clock-synchronized read signal responsive to the latency information comprises:
receiving the system clock signal and the plurality of first timing control signals; and
providing pointer output signals by decoding the plurality of first timing control signals responsive to the system clock signal.

Assignees

• Micron Technology Inc

Inventors

• Ishibashi Shuichi
• Miyano Kazutaka
• Fujisawa Hiroki

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/225 Primary

  Clock input buffers · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/109

  Control signal input circuits · CPC title