Semiconductor device, system, and method for operating system

Patent metadata

Field	Value
Publication number	US-10290253-B2
Application number	US-201715615997-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Jun 10, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An object is to provide a semiconductor device that automatically adjusts the luminance of a display device. The semiconductor device includes an illuminometer, a threshold detector, a timing controller, a digital-to-analog converter circuit, a first display panel, and a second display panel. The illuminance of external light is measured with the illuminometer, and the threshold value of digital video data is determined by the threshold detector in accordance with the illuminance. The timing controller generates a signal for the first display panel or a signal for the second display panel on the basis of the threshold value and video data transmitted from the outside. The signal for the first display panel and the signal for the second display panel are input to one digital-to-analog converter circuit and converted into digital signals, and the obtained digital signals are input to a corresponding one of the first display panel and the second display panel.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first circuit comprising a first terminal, a second terminal, a first output terminal, and a resistor string;
a second circuit comprising a third terminal, a fourth terminal, a second output terminal, and a resistor string;
a pass transistor logic circuit comprising a first input terminal, a second input terminal, a third input terminal, and a third output terminal;
a first switch;
a second switch; and
a selector comprising a fourth input terminal, a fourth output terminal, and a fifth output terminal,
wherein:
the third terminal of the second circuit is electrically connected to one terminal of the first switch,
the second terminal of the first circuit is electrically connected to the other terminal of the first switch,
one terminal of the second switch is electrically connected to the fourth terminal of the second circuit,
the other terminal of the second switch is electrically connected to the second terminal of the first circuit,
the first output terminal of the first circuit is electrically connected to the first input terminal of the pass transistor logic circuit,
the second output terminal of the second circuit is electrically connected to the second input terminal of the pass transistor logic circuit,
the third output terminal of the pass transistor logic circuit is electrically connected to the fourth input terminal of the selector, and
when digital data is input to the third input terminal of the pass transistor logic circuit, the digital data is converted into analog data, and the analog data is output from one of the fourth output terminal and the fifth output terminal of the selector.

2. The semiconductor device according to claim 1 , further comprising a third circuit between an electrical connection between the third output terminal of the pass transistor logic circuit and the fourth input terminal of the selector, the third circuit comprising a fifth input terminal and a sixth output terminal,
wherein:
the fifth input terminal of the third circuit is electrically connected to the third output terminal of the pass transistor logic circuit,
the sixth output terminal of the third circuit is electrically connected to the fourth input terminal of the selector, and
the third circuit is configured to amplify a potential input to the fifth input terminal of the third circuit and output the amplified potential to the sixth output terminal of the third circuit.

3. The semiconductor device according to claim 2 ,
wherein the third circuit further comprises a fifth terminal, and
wherein the third circuit is configured to stop operating in accordance with a potential input to the fifth terminal of the third circuit.

4. The semiconductor device according to claim 1 , further comprising a third switch between an electrical connection between the third output terminal of the pass transistor logic circuit and the fourth input terminal of the selector,
wherein one terminal of the third switch is electrically connected to the third output terminal of the pass transistor logic circuit, and
wherein the other terminal of the third switch is electrically connected to the fourth input terminal of the selector.

5. The semiconductor device according to claim 4 ,
wherein the third switch comprises a first transistor, and
wherein a channel formation region of the first transistor comprises an oxide containing at least one of indium, an element M, and zinc, where the element M is one of aluminum, gallium, yttrium, and tin.

6. The semiconductor device according to claim 1 , further comprising a third switch and a third circuit between an electrical connection between the third output terminal of the pass transistor logic circuit and the fourth input terminal of the selector, the third circuit comprising a fifth input terminal and a sixth output terminal,
wherein:
the fifth input terminal of the third circuit is electrically connected to the third output terminal of the pass transistor logic circuit,
the sixth output terminal of the third circuit is electrically connected to one terminal of the third switch,
the other terminal of the third switch is electrically connected to the fourth input terminal of the selector, and
the third circuit is configured to amplify a potential input to the fifth input terminal of the third circuit and output the amplified potential to the sixth output terminal of the third circuit.

7. The semiconductor device according to claim 6 ,
wherein the third switch further comprises a first transistor, and
wherein a channel formation region of the first transistor comprises an oxide containing at least one of indium, an element M, and zinc, where the element M is one of aluminum, gallium, yttrium, and tin.

8. The semiconductor device according to claim 2 ,
wherein:
the third circuit further comprises an operational amplifier,
the fifth input terminal of the third circuit is electrically connected to a non-inverting input terminal of the operational amplifier,
the sixth output terminal of the third circuit is electrically connected to an output terminal of the operational amplifier, and
the output terminal of the operational amplifier is electrically connected to an inverting input terminal of the operational amplifier.

9. The semiconductor device according to claim 1 ,
wherein:
the first circuit further comprises a first resistor and a second resistor,
the second circuit further comprises a third resistor and a fourth resistor,
the first output terminal of the first circuit comprises a fifth terminal and a sixth terminal,
the second output terminal of the second circuit comprises a seventh terminal and an eighth terminal,
the first terminal of the first circuit is electrically connected to one terminal of the first resistor,
the other terminal of the first resistor is electrically connected to one terminal of the second resistor,
the other terminal of the second resistor is electrically connected to the second terminal of the first circuit,
the fifth terminal is electrically connected to the one terminal of the first resistor,
the sixth terminal is electrically connected to the one terminal of the second resistor,
the third terminal of the second circuit is electrically connected to one terminal of the third resistor,
the other terminal of the third resistor is electrically connected to one terminal of the fourth resistor,
the other terminal of the fourth resistor is electrically connected to the fourth terminal of the second circuit,
the seventh terminal is electrically connected to the one terminal of the third resistor, and
the eighth terminal is electrically connected to the one terminal of the fourth resistor.

10. The semiconductor device according to claim 1 ,
wherein the first switch and the second switch each comprise a second transistor, and
wherein a channel formation region of the second transistor comprises an oxide containing at least one of indium, an element M, and zinc, where the element M is one of aluminum, gallium, yttrium, and tin.

11. The semiconductor device according to claim 1 , further comprises a fourth switch and a fifth switch,
wherein one terminal of the fourth switch is electrically connected to the fourth terminal, and
wherein one terminal of the fifth switch is electrically connected to the fourth terminal.

12. A system comprising:
the semiconductor device according to claim 1 ;
an illuminometer;
a fourth circuit;
a fifth circuit;
a first display panel; and
a second display panel,
wherein:
the illuminometer is electrically connected to the fourth circuit,
the fourth circuit

Assignees

• Semiconductor Energy Lab

Inventors

• Inoue Tatsunori
• Aoki Takeshi

Classifications

• G09G2300/046

  with an emissive area and a light-modulating area combined in one pixel · CPC title

• H01L27/1225

  Electricity · mapped topic

• G09G3/2007 Primary

  Display of intermediate tones · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3225

  using an active matrix · CPC title