Reset domain crossing management using unified power format

Patent metadata

Field	Value
Publication number	US-10289773-B2
Application number	US-201715633542-A
Country	US
Kind code	B2
Filing date	Jun 26, 2017
Priority date	Jun 30, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.

First claim

What is claimed is:

1. A method of efficiently addressing reset domain crossings (RDCs) and power domain crossings (PDCs) in an initial circuit design, said initial circuit design including a plurality of circuit structures and a plurality of signals passing between said plurality of circuit structures, said initial circuit design being defined by an initial Hardware Description Language (HDL) description in which each of said plurality of circuit structures is assigned to an associated reset domain of a plurality of reset domains such that one or more of said plurality of signals forms a corresponding said RDC between two reset domains of said plurality of reset domains, said initial circuit design being further defined by an initial Unified Power Format (UPF) description in which each of said plurality of circuit structures is further assigned to an associated power domain of a plurality of power domains such that one or more of said plurality of signals forms a corresponding said PDC between two power domains of said plurality of power domains, the method comprising:
utilizing both said initial HDL description and said initial UPF description to identify at least one signal of said plurality of signals that forms both a corresponding said RDC and a corresponding said PDC;
generating a report indicating that said at least one signal is a candidate for a shared RDC/PDC isolation structure.

2. The method of claim 1 , wherein utilizing both said initial HDL description and said initial UPF description comprises:
selecting a signal of said plurality of signals that forms a corresponding RDC in said initial HDL description;
analyzing said initial UPF description to determine whether said selected signal also forms a corresponding PDC.

3. The method of claim 2 , wherein utilizing both said initial HDL description and said initial UPF description further comprises determining whether said corresponding PDC includes an associated isolation resource.

4. The method of claim 3 , wherein determining whether said corresponding PDC includes an associated isolation resource further comprises determining whether said associated isolation resource is compatible with said corresponding RDC.

5. The method of claim 2 , further comprising determining whether said selected signal is associated with one of isolation resources and synchronization resources in said initial HDL description.

6. The method of claim 5 , wherein said determining is performed before said analyzing said initial UPF description.

7. The method of claim 1 , wherein utilizing both said initial HDL description and said initial UPF description comprises utilizing the initial HDL description to generate a modified UPF description in which reset domains identified in the initial HDL description are modeled as pseudo-power domains in the modified UPF description, and said signals forming said RDCs in said initial HDL description are identified as pseudo-power domain crossings in the modified UPF description.

8. The method of claim 7 , wherein utilizing the initial HDL description to generate said modified UPF description comprises generating said modified UPF description separate from said initial UPF description.

9. The method of claim 7 , wherein utilizing the initial HDL description to generate said modified UPF description comprises generating said modified UPF description including both said plurality of power domains of said initial UPF description and said pseudo-power domains.

10. The method of claim 7 , further comprising utilizing said modified UPF description to automatically generate RDC isolation solutions.

11. A method for verifying a circuit design utilized to fabricate an integrated circuit (IC), the circuit design including a plurality of reset domains and power domains, the method comprising utilizing a Unified Power Format (UPF) description of the circuit design and a Hardware Description Language (HDL) description of the circuit design to identify at least one signal that forms a reset domain crossing (RDC) by way of being transmitted between two reset domains of said plurality of reset domains, and also forms a power domain crossing (PDC) by way of being transmitted between two power domains of said plurality of power domains.

12. The method of claim 11 , further comprising generating a report indicating that said at least one signal is a candidate for a shared RDC/PDC isolation structure.

13. The method of claim 11 , further comprising automatically generating a shared RDC/PDC isolation structure for said at least one signal.

14. The method of claim 11 , wherein utilizing said UPF description comprises:
selecting a signal of said plurality of signals that forms a corresponding RDC in an initial HDL description of said circuit design; and
analyzing said UPF description to determine whether said selected signal also forms a corresponding said PDC.

15. The method of claim 14 , wherein utilizing said UPF description further comprises determining whether said corresponding PDC includes an associated isolation resource.

16. The method of claim 15 , wherein determining whether said corresponding PDC includes an associated isolation resource further comprises determining whether said associated isolation resource is compatible with said corresponding RDC.

17. The method of claim 11 , wherein utilizing said UPF description comprises utilizing an HDL description of said circuit design to generate a modified UPF description in which reset domains identified in the HDL description are modeled as pseudo-power domains in the modified UPF description, and said at least one signal forming said corresponding RDC in said HDL description is identified as a pseudo-power domain crossing in the modified UPF description.

18. The method of claim 17 , wherein utilizing the HDL description to generate said modified UPF description comprises generating said modified UPF description separate from said initial UPF description.

19. The method of claim 17 , wherein utilizing the HDL description to generate said modified UPF description comprises generating said modified UPF description including both said plurality of power domains and said pseudo-power domains.

20. A non-transitory, computer-readable medium storing an EDA software tool including computer-executable instructions configured such that, when the EDA software tool is executed by a processor, cause the processor to execute a process comprising a method for verifying a circuit design utilized to fabricate an integrated circuit (IC), the circuit design including a plurality of reset domains and power domains, said verifying method including analyzing a Unified Power Format (UPF) description of the circuit design and a Hardware Description Language (HDL) description of the circuit design to identify at least one signal of the circuit design that forms a reset domain crossing (RDC) by way of being transmitted between two reset domains of said plurality of reset domains, and also forms a power domain crossing (PDC) by way of being transmitted between two power domains of said plurality of power domains.

Assignees

• Synopsys Inc

Inventors

• Shah Deep
• Gupta Namit
• Sarwary Mohamed Shaker

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/396

  Clock trees · CPC title

• G06F17/505

  Physics · mapped topic

• G06F2217/62

  Physics · mapped topic

• G06F17/5022 Primary

  Physics · mapped topic