Memory processing core architecture

Patent metadata

Field	Value
Publication number	US-10289604-B2
Application number	US-201414453990-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Aug 7, 2014
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Aspects of the present invention provide a memory system comprising a plurality of stacked memory layers, each memory layer divided into memory sections, wherein each memory section connects to a neighboring memory section in an adjacent memory layer, and a logic layer stacked among the plurality of memory layers, the logic layer divided into logic sections, each logic section including a memory processing core, wherein each logic section connects to a neighboring memory section in an adjacent memory layer to form a memory vault of connected logic and memory sections, and wherein each logic section is configured to communicate directly or indirectly with a host processor. Accordingly, each memory processing core may be configured to respond to a procedure call from the host processor by processing data stored in its respective memory vault and providing a result to the host processor. As a result, increased performance may be provided.

First claim

We claim:

1. A memory system for a host processor executing an application program, the memory system comprising:
a plurality of physically continuous memory layers, each memory layer providing for data storage and divided into memory sections, wherein memory sections of each layer are vertically, electrically connected to other memory sections in other memory layers in a physical stack to form a plurality of separate memory columns communicating through the memory column; and
a logic layer divided into logic sections, each logic section including at least one memory processing core, the memory processing core providing for fetch, decode, and execute cycles during which instructions are fetched and executed, wherein each logic section connects to a corresponding memory column to form a memory vault of connected logic and memory sections operable in parallel, and wherein each logic section further includes communication logic configured to communicate directly or indirectly with the host processor;
wherein each memory processing core is configured to respond to a procedure call from the host processor designating a set of application code instructions and a target address of a given memory by:
(a) receiving the set of instructions of the application program being executed by the host processor at the given memory vault, wherein the set of instructions is configured to be executed by a memory processing core of the given memory vault using data from the memory column of the data vault as a procedure call;
(b) retrieving data stored in a memory column connected to a logic section including the memory processing core;
(c) executing the set of instructions designated by the procedure call with the data to produce a result; and
(d) providing the result back to the host processor in response to the procedure call.

2. The memory system of claim 1 , wherein each logic section provides for multiple independent memory processing cores each providing for fetch, decode, and execute cycles during which instructions are fetched and executed,
wherein each memory processing core is configured to respond to different procedure calls from the host processor, and
wherein the host processor executes the application code divided into a plurality of partitions, and each partition is allocated for storage in a memory vault.

3. The memory system of claim 1 , wherein each logic section includes at least one memory processing core per memory layer.

4. The memory system of claim 1 , further comprising a compute scheduler in each logic section, wherein the compute scheduler assigns the procedure call to a next available memory processing core.

5. The memory system of claim 1 , wherein each memory section comprises a plurality of DRAM memory banks.

6. The memory system of claim 5 , wherein each logic section includes at least one memory processing core per DRAM memory bank.

7. The memory system of claim 1 , wherein clock frequencies of the memory processing cores are less than a clock frequency of the host processor.

8. The memory system of claim 1 , further comprising at least first and second memory processing cores associated with each memory vault, wherein the memory system is configured to enable execution of a later procedure call by a first memory processing core before execution of an earlier procedure call by a second memory processing core.

9. The memory system of claim 1 , wherein the logic layer is stacked among the plurality of memory layers, and wherein the memory vaults are connected by through-silicon vias.

10. A computer system comprising:
a host processor comprising at least one host processing core and a memory processing controller and adapted to execute an application program of instructions;
a plurality of physically continuous memory layers, each memory layer providing for data storage and divided into memory sections, wherein memory sections of each layer are vertically, electrically connected to other memory sections in other memory layers in a physical stack to form a plurality of separate memory columns communicating through the memory column; and
a logic layer divided into logic sections, each logic section including at least one memory processing core, the memory processing core providing for fetch, decode, and execute cycles during which instructions are fetched and executed, wherein each logic section connects to a corresponding memory column to form an addressable memory vault of connected logic and memory sections operable in parallel, and wherein each logic section further includes communication logic in communication with the host processor through the memory processing controller;
wherein the host processor communicates procedure calls, designating sets of application code instructions and a target address of a given memory vault, to the memory processing controller, and the memory processing controller routes the procedure calls directly or indirectly to memory processing cores based on the target addresses of the procedure calls corresponding to memory vaults of the memory processing cores; and
wherein the memory processing cores respond to the procedure calls by:
(a) receiving the sets of instructions of the application program being executed by the host processor, wherein the set of instructions are configured to be executed by a memory processing core of a memory vault of a target address using data from the memory column of the data vault as a procedure call;
(b) retrieving data stored in memory columns connected directly without intervening cache structures to logic sections including the memory processing cores;
(c) executing the sets of instructions designated by the procedure call with the data to produce results; and
(d) providing the results back to the host processor in response to the procedure calls.

11. The computer system of claim 10 , wherein the host processor executes the application code divided into partitions, wherein each partition is allocated for storage in a memory vault and the procedure call refers to the first and second partition.

12. The computer system of claim 10 , wherein each logic section includes at least one memory processing core per memory layer.

13. The computer system of claim 12 , further comprising a compute scheduler in each logic section, wherein the compute scheduler assigns procedure calls to next available memory processing cores.

14. The computer system of claim 10 , wherein each memory section comprises a plurality of DRAM memory banks.

15. The computer system of claim 14 , wherein each logic section includes at least one memory processing core per DRAM memory bank.

16. The computer system of claim 10 , wherein clock frequencies of the memory processing cores are less than a clock frequency of the host processor.

17. The computer system of claim 10 , further comprising at least first and second memory processing cores in a memory vault, wherein the memory vault is configured to enable execution of a later procedure call by a first memory processing core before execution of an earlier procedure call by a second memory processing core.

18. The computer system of claim 10 , wherein the logic layer is stacked among the plurality of memory layers, and wherein the memory vaults are connected using through-silicon vias.

19. The computer system of claim 10 , wherein the host processor queues a plurality of procedure calls in a single thread, and wherein a plurality of memory processing cores each execute a thread for responding to a procedure call.

20. A met

Assignees

• Wisconsin Alumni Res Found

Inventors

• Sankaralingam Karthikeyan
• Menon Jaikrishnan
• De Carli Lorenzo

Classifications

• G06F15/7821 Primary

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title

• Y02D10/12

  Cross-Sectional Technologies · mapped topic

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title