Storage system and method for flush optimization

US10289552B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10289552-B2
Application numberUS-201715611510-A
CountryUS
Kind codeB2
Filing dateJun 1, 2017
Priority dateMay 3, 2017
Publication dateMay 14, 2019
Grant dateMay 14, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A storage system and method are provided for flush optimization. In one embodiment, a storage system is provided comprising a cache, a non-volatile memory, and a controller. The controller is configured to: store, in the cache, data received from a host and to be written in the non-volatile memory; receive a command from the host to move the data stored in the cache into the non-volatile memory; without having executed the command, send a confirmation to the host that the command was executed; and execute the command after sending the continuation to the host.

First claim

Opening claim text (preview).

What is claimed is: 1. A storage system comprising: a cache; a non-volatile memory; and a controller in communication with the cache and the non-volatile memory, wherein the controller is configured to: store, in the cache, data received from a host and to be written in the non-volatile memory; receive a command from the host to move the data stored in the cache into the non- volatile memory; without having executed the command, send a confirmation to the host that the command was executed; and execute the command after sending the confirmation to the host, wherein the controller is configured to send the confirmation to the host only after receiving, from the host, an indication that the data in the cache is safe from loss due to power failure. 2. The storage system of claim 1 , wherein the indication indicates that the host's battery is un-removable and indicates the power charging level of the host's battery. 3. The storage system of claim 1 , wherein the controller is configured to execute the command after an expiration of a time delay. 4. The storage system of claim 3 further comprising a capacitor configured to hold enough charge to power the storage system for more than the time delay. 5. The storage system of claim 3 , wherein a length of the time delay is set by the host. 6. The storage system of claim 1 , wherein the cache comprises storage class memory. 7. The storage system of claim 1 further comprising a write command queue, and wherein the controller is further configured to: prior to executing the command to move the data: determine if there is a write command in the write command queue; and in response to determining there is a write command in the write command queue, store, in the cache, data associated with the write command. 8. The storage system of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory. 9. The storage system of claim 1 , wherein the storage system is embedded in the host. 10. The storage system of claim 1 , wherein the storage system is removably connected to the host. 11. A method for executing a flush command, the method comprising: performing the following in a storage system in communication with a host, wherein the storage system comprises a write cache: receiving a command from the host to flush the write cache; sending an acknowledgement to the host that the cache was flushed even though the write cache was not flushed; after a period of time after sending the acknowledgement, flushing the write cache, wherein the data flushed from the write cache after the period of time is different from the data that would have been flushed if the write cache was flushed prior to sending the acknowledgement; and before sending the acknowledgement, receiving an indication from the host that the data in the write cache will not be lost due to power failure. 12. The method of claim 11 , wherein the indication indicates that the host's battery is un-removable and indicates the power charging level of the host's battery. 13. The method of claim 11 further comprising prior to flushing the write cache: determining if there is a write command in a write command queue in the storage system; and in response to determining there is a write command in the write command queue, storing, in the write cache, data associated with the write command. 14. The method of claim 11 , wherein the write cache is flushed into a non-volatile, three-dimensional memory of the storage system. 15. The method of claim 11 , wherein the storage system is embedded in the host. 16. The method of claim 11 , wherein the storage system is removably connected to the host. 17. A storage system comprising: a cache; a non-volatile memory; and means for sending a confirmation of execution of a flush command to a host even though the flush command was not executed, wherein the confirmation is sent after receiving, from the host, an assurance that there will not be a power loss from the host prior to the storage system later executing the flush command. 18. The storage system of claim 17 , wherein the assurance comprises an indication that indicates that the host's battery is un-removable and the power charging level of the host's battery. 19. The storage system of claim 17 , wherein the non-volatile memory comprises a three-dimensional memory.

Assignees

Inventors

Classifications

  • Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

  • using clearing, invalidating or resetting means · CPC title

  • Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

  • Multiuser, multiprocessor or multiprocessing cache systems · CPC title

  • with main memory updating (G06F12/0806 takes precedence) · CPC title

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What does patent US10289552B2 cover?
A storage system and method are provided for flush optimization. In one embodiment, a storage system is provided comprising a cache, a non-volatile memory, and a controller. The controller is configured to: store, in the cache, data received from a host and to be written in the non-volatile memory; receive a command from the host to move the data stored in the cache into the non-volatile memory…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0868. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 14 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).