Reliability enhancement utilizing speculative execution systems and methods

Patent metadata

Field	Value
Publication number	US-10289469-B2
Application number	US-201615338247-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Oct 28, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.

First claim

What is claimed is:

1. A system comprising:
a processor configured to execute program instructions and incident thereto to perform reliability enhancement operations, wherein the reliability enhancement operations comprise:
identifying functionality of a particular portion of the program instructions;
speculatively executing multiple sets of operations contemporaneously, wherein the multiple sets of operations are functional duplicates of the particular portion of the program instructions, to generate at least a first result and a second result;
comparing speculative execution results from the multiple sets of operations to generate a comparison of the first result against the second result to produce a comparison result; and
performing an error mitigation operation in response to a comparison mismatch in execution results of the comparison result; and
a memory configured to store information for the processor.

2. The system of claim 1 , wherein the reliability enhancement operations further comprise making the execution results architecturally visible if the execution results from the multiple sets of operations have a matching value.

3. The system of claim 1 , wherein the error mitigation operation comprises a corrective procedure.

4. The system of claim 3 , wherein the error mitigation operation comprises a rollback to a known valid state.

5. The system of claim 1 , wherein the multiple sets of operations correspond to multiple sets of native machine instructions.

6. The system of claim 5 , further comprises a conversion component configured to convert non-native instructions into the multiple sets of native machine instructions.

7. The system of claim 6 , wherein the conversion component converts ARM architectural code corresponding to the particular portion of the program instructions into the multiple sets of native machine instructions.

8. The system of claim 6 , wherein the conversion component converts RISC architectural code corresponding to the particular portion of the program instructions into the multiple sets of native machine instructions.

9. The system of claim 6 , wherein the conversion component converts X86 architectural code corresponding to the particular portion of the program instructions into the multiple sets of native machine instructions.

10. The system of claim 6 , wherein the conversion component converts CISC architectural code corresponding to the particular portion of the program instructions into the multiple sets of native instructions.

11. The system of claim 6 , wherein the conversion component converts GPU shader assembly code corresponding to the particular portion of the program instructions into the multiple sets of native instructions.

12. The system of claim 6 , wherein the multiple sets of native instructions are optimized.

13. The system of claim 1 , wherein input values to stores are compared.

14. The system of claim 1 , wherein the processor is a central processing unit (CPU).

15. The system of claim 1 , wherein the processor is a graphics processing unit (GPU).

16. A method of reliability enhancement, said method comprising:
performing an instruction parsing process, comprising determining a functionality associated with program instructions;
executing the program instructions and incident to executing the program instructions performing fault checking, wherein the fault checking comprises:
speculatively executing multiple sets of operations contemporaneously, wherein the multiple sets of operations are functional duplicates of the program instructions; and
comparing results from the speculative execution; and performing error mitigation based on a mismatch result from the comparison,

wherein the fault checking further comprises:
storing an initial storage value from a first register to a first storage location;
loading a return storage value back from the first storage location, wherein the return storage value is loaded in a second register;
comparing the initial storage value in the first register and the return storage value in the second register; and
performing additional error mitigation based on a mismatch in the initial storage value in the first register and the return storage value in the second register.

17. The method of reliability enhancement of claim 16 , wherein the results are made architecturally visible if the comparing matches.

18. The method of reliability enhancement of claim 16 , wherein the error mitigation comprises correcting errors.

19. The method of reliability enhancement of claim 16 , wherein said fault checking further comprises committing said results if the comparing matches and rolling back to a known valid state if the comparing does not match.

20. The method of reliability enhancement of claim 16 , further comprising preparing native machine instructions for execution.

21. The method of reliability enhancement of claim 16 , wherein the fault checking further comprises fault checking load and storage paths.

22. The method of reliability enhancement of claim 16 , wherein the comparing further comprises comparing results of load operations associated with the particular code portion.

23. The method of reliability enhancement of claim 16 , wherein values that are made architecturally visible are stored and wherein the fault checking further comprises checking storage.

24. The method of reliability enhancement of claim 16 , wherein the comparing further comprises comparing input branch values.

25. A computer readable medium with instructions encoded thereon that when executed by a processor perform:
conversion and optimization of a particular code portion to produce native machine instructions, wherein the native machine instructions are functional duplicates of the particular code portion, corresponding to at least a first result and a second result;
self checking contemporaneous speculative execution of the native machine instructions of the first result and second result to produce a comparison result; and
error mitigation based upon the self-checking speculative execution of the comparison result.

26. The computer readable medium of claim 25 , wherein the conversion and optimization of a particular code portion comprises creating multiple instruction streams of the native machine instructions.

27. The computer readable medium of claim 26 , wherein the self-checking speculative execution includes:
speculatively executing the multiple instruction streams contemporaneously; and
comparing results of the multiple instruction streams of code portions.

28. The computer readable medium of claim 27 , wherein the error mitigation is performed responsive to a mismatch in the comparing.

29. The computer readable medium of claim 25 , wherein the conversion and optimization of a particular code portion produces multiple sets of native machine instructions that are functional duplicates of the particular code portion.

30. A method of executing a program, said method comprising:
converting said program comprising instructions of a high level language into a plurality of instructions that are native to a processor, said plurality of instructions for execution on said processor, wherein a portion of said program is converted into a first code portion of native machine instructions and a second code portion of native machine instr

Assignees

• Nvidia Corp

Inventors

• Fortino Nick
• Gruner Fred
• Hertzberg Ben

Classifications

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title