Apparatus and method for increasing resilience to faults

Patent metadata

Field	Value
Publication number	US-10289332-B2
Application number	US-201715493609-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.

First claim

We claim:

1. An apparatus comprising:
processing circuitry to execute a plurality of code sequences including at least one critical code sequence; and
configuration storage to store mode control data for the processing circuitry;
when the processing circuitry is executing said at least one critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to resilience of the processing circuitry in a default mode of operation, wherein:
the processing circuitry comprises a first subset of components required for correct execution of instructions of each code sequence, and a second subset of components whose usage is unnecessary for correct execution of said instructions; and
the one or more components whose usage is modified when the processing circuitry is in the high resilience mode comprise components within said second subset.

2. An apparatus as claimed in claim 1 , wherein:
the processing circuitry comprises a first subset of components required for correct execution of instructions of each code sequence, and a second subset of components whose usage is unnecessary for correct execution of said instructions; and
the one or more components whose usage is modified when the processing circuitry is in the high resilience mode comprise components within said second subset.

3. An apparatus as claimed in claim 1 , wherein one or more of the components in said second subset are provided to seek to improve performance of the processing circuitry.

4. An apparatus as claimed in claim 1 , wherein the modification in the usage of the one or more components when the processing circuitry is in said high resilience mode comprises one of:
bypassing the component;
decreasing an extent to which the component is used;
disabling the component.

5. An apparatus as claimed in claim 1 , wherein:
the processing circuitry comprises fetch circuitry to fetch the instructions of each code sequence from a memory system prior to execution of those instructions, the memory system employing an error detection scheme; and
when in the high resilience mode of operation, usage of the fetch circuitry is modified to cause the fetch circuitry to reduce a fetch rate relative to a fetch rate used when the processing circuitry is in the default mode of operation.

6. An apparatus as claimed in claim 5 , wherein:
said one or more components comprise at least one buffer structure used to buffer information derived from the fetched instructions prior to execution of the instructions; and
when in the high resilience mode of operation, the usage of said at least one buffer structure is modified to reduce an effective size of the at least one buffer structure relative to the effective size when in the default mode of operation, to thereby reduce the fetch rate of the fetch circuitry.

7. An apparatus as claimed in claim 1 , wherein:
the modification in the usage of said one or more components of the processing circuitry takes into account at least one characteristic of the critical code sequence, such that an impact on performance of the processing circuitry when executing the critical code sequence in the high resilience mode of operation is less than a first threshold.

8. An apparatus as claimed in claim 7 , wherein said at least one characteristic comprises at least one of:
a proportion of memory access instructions above a second threshold;
a proportion of branch instructions below a third threshold;
such that a reduction in a fetch rate of instructions by fetch circuitry of the processing circuitry has an impact on performance less than said first threshold.

9. An apparatus as claimed in claim 1 , wherein:
the processing circuitry is arranged to be coupled to a memory system that employs an error detection scheme;
the memory system comprises a first memory within which at least one of the critical code sequence and data used by the critical code sequence is stored, the processing circuitry being arranged, when executing the critical code sequence, to directly access the first memory bypassing at least one cache memory of the memory system, said at least one cache memory including one or more components unprotected by the error detection scheme.

10. An apparatus as claimed in claim 9 , wherein the first memory is a tightly coupled memory (TCM).

11. An apparatus as claimed in claim 1 , wherein the processing circuitry is arranged to be coupled to a memory system that employs an error detection scheme, further comprising:
data access buffer circuitry to buffer data access operations to be performed within the memory system; and
when in the high resilience mode of operation, the usage of said data access buffer circuitry is modified to reduce a latency of the data access buffer circuitry relative to its latency when in the default mode of operation.

12. An apparatus as claimed in claim 11 , wherein the latency is reduced by reducing an effective size of the data access buffer circuitry relative to the effective size when in the default mode of operation.

13. An apparatus as claimed in claim 1 , wherein:
the processing circuitry is coupled to a memory system that employs an error detection scheme;
the critical code sequence is a memory scrubbing routine executed to read content from the memory system, correct any identified faults that are correctable in accordance with the error detection scheme, and then rewrite the content back to the memory system, thereby seeking to prevent accumulation of faults within the memory system.

14. An apparatus as claimed in claim 13 , wherein the error detection scheme is an error correction code (ECC) scheme.

15. An apparatus as claimed in claim 1 , wherein:
the processing circuitry is coupled to a memory system that employs an error detection scheme;
the critical code sequence is a check-pointing routine executed to save to the memory system architectural state of a program being executed by the processing circuitry, to allow rollback to that saved architectural state on detection of an error within the processing circuitry.

16. An apparatus as claimed in claim 15 , further comprising:
at least one further processing circuitry arranged to operate in lockstep with the processing circuitry to provide redundant processing of program instructions; and
when performing the check-pointing routine, both the processing circuitry and the at least one further processing circuitry are placed in the high resilience mode of operation to reduce probability of an error being detected during performance of the check-pointing routine.

17. An apparatus as claimed in claim 1 , further comprising:
at least two further processing circuitries arranged to operate in lockstep with said processing circuitry to perform redundant processing of program instructions;
error detection circuitry to detect a mismatch between signals on a corresponding signal node in said processing circuitry and said at least two further processing circuitries;
wherein, in response to detecting said mismatch, the error detection circuitry is configured to trigger a recovery routine for resolving an error detected for an erroneous processing circuitry using state information derived from at least two other processing circuitries;
said recovery routine forming said critical code sequence, such that said processing circuitry and said at least two further processing circuitries

Assignees

• Advanced Risc Mach Ltd

Inventors

• Iturbe Xabier
• Özer Emre
• VENU Balaji
• Penton Antony John

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F3/0634 Primary

  by changing the state or mode of one or more devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title