Electronic device display with switchable film structures

Patent metadata

Field	Value
Publication number	US-10288935-B2
Application number	US-201615064097-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Jun 3, 2015
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The display may be operated in at least a normal viewing mode, a privacy mode, an outdoor viewing mode, and a power saving mode. The different view modes may exhibit different viewing angles. In one configuration, the display may include a switchable phase retarder that can be selectively activated to help reduce contrast ratios at higher viewing angles. A rotated pixel design that includes one or more groups of parallel fingers can be used to help properly align the low contrast regions. In another configuration, the display may include multiple electrically controlled birefringence (ECB) layers that can be selectively activated to provide a desired cone of vision, a region outside of which exhibits substantially reduced contrast ratios.

First claim

What is claimed is:

1. An electronic device display, comprising:
a switchable phase retarder that is configured in an isotropic state when the electronic device display is operated in a normal viewing mode and that is configured in an anisotropic state when the electronic device display is operated in a privacy mode to provide a contrast profile having low contrast regions and high contrast regions, wherein the display is coplanar with an X-Y plane; and
display layers having thin-film transistor structures, wherein the display layers comprise parallel pixel finger electrodes shorted by a conductive sidebar, wherein the parallel pixel finger electrodes are tilted at an angle with respect to the conductive sidebar so that the low contrast regions are positioned at viewing angles of 0° and 180° in the X-Y plane during the privacy mode, and wherein the angle is within a range of 10° to 55°.

2. The electronic device display of claim 1 , further comprising:
an upper polarizer; and
a lower polarizer, wherein the switchable phase retarder is interposed between the upper polarizer and the display layers.

3. The electronic device display of claim 1 , further comprising:
an upper polarizer; and
a lower polarizer, wherein the switchable phase retarder is interposed between the lower polarizer and the display layers.

4. The electronic device display of claim 1 , wherein the switchable phase retarder comprises blue phase liquid crystal material.

5. The electronic device display of claim 1 , wherein the switchable phase retarder provides reduced contrast ratios at viewing angles greater than 30° during the privacy mode.

6. The electronic device display of claim 1 , wherein the switchable phase retarder receives a bias voltage during the privacy mode such that the switchable phase retarder is configured to provide a predetermined amount of phase retardation.

7. The electronic device display of claim 1 , wherein the angle is 35°.

8. An electronic device display, comprising:
display layers having thin-film transistor structures, wherein the display layers comprise parallel pixel finger electrodes, wherein the parallel pixel finger electrodes are shorted by a conductive crossbar that is perpendicular to the parallel pixel finger electrodes, and wherein the conductive crossbar bisects only one of the parallel pixel finger electrodes into two equal and colinear segments; and
a switchable phase retarder that is configured in an isotropic state when the electronic device display is operated in a normal viewing mode and that is configured in an anisotropic state when the electronic device display is operated in a privacy mode.

9. The electronic device display of claim 8 , wherein the conductive crossbar and the parallel pixel finger electrodes have different widths.

10. An electronic device display, comprising:
display layers having thin-film transistor structures, wherein the display layers comprise:
a switchable phase retarder that is configured in an isotropic state when the electronic device display is operated in a normal viewing mode and that is configured in an anisotropic state when the electronic device display is operated in a privacy mode to provide a contrast profile;
a conductive crossbar;
a first set of parallel pixel electrode fingers formed at a first non-obtuse angle with respect to the conductive crossbar; and
a second set of parallel pixel electrode fingers formed at a second non-obtuse angle with respect to the conductive crossbar, wherein the second non-obtuse angle is different than the first non-obtuse angle, and wherein the first and second sets of parallel pixel electrode fingers are shorted to the conductive crossbar.

11. The electronic device display of claim 10 , wherein the first non-obtuse angle is equal to 90 degrees.

12. The electronic device display of claim 11 , wherein the second non-obtuse angle is less than 90 degrees.

13. The electronic device display of claim 1 , wherein the low contrast regions are further positioned at viewing angles of 90° and 270° in the X-Y plane during the privacy mode.

14. The electronic device display of claim 1 , wherein the high contrast regions are positioned at viewing angles of 45° and 135° in the X-Y plane during the privacy mode.

Assignees

• Apple Inc

Inventors

• Choi Hyungryul J
• Jiang Shih-Chyuan Fan
• Carbone Giovanni

Classifications

• G02F1/133526

  Lenses, e.g. microlenses or Fresnel lenses · CPC title

• G02F1/1334

  based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/1393

  the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells (G02F1/1396, G02F1/141 take precedence) · CPC title

• G02F2203/50

  Phase-only modulation · CPC title