MTJ-based temperature-sensing device

Patent metadata

Field	Value
Publication number	US-10288494-B2
Application number	US-201715591976-A
Country	US
Kind code	B2
Filing date	May 10, 2017
Priority date	Nov 30, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A thermometer circuit configured to estimate a monitored temperature is disclosed. The circuit includes an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value; a plurality of gated conductors coupled to the resistor; and a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature.

First claim

What is claimed is:

1. A thermometer circuit configured to estimate a monitored temperature, comprising:
an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value;
a plurality of gated conductors coupled to the resistor; and
a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature, wherein when the first current signal is generated, gate terminals of the plurality of gated conductors are electrically coupled to the resistor and when the second current signal is generated, the gate terminals of the plurality of gated conductors are electrically decoupled from the resistor.

2. The circuit of claim 1 , wherein the resistor includes a magnetic tunnel junction (MTJ) cell.

3. The circuit of claim 2 , wherein the resistor presents the first resistance value when the MTJ cell is in a parallel state, and the resistor presents the second resistance value when the MTJ cell is in an anti-parallel state.

4. The circuit of claim 1 , further comprising:
a comparator coupled to the plurality of gated conductors and the resistor; and
a plurality of switches, wherein each switch is coupled between the resistor and a respective gated conductor, and wherein each switch is turned off to deactivate the respective gated conductor.

5. The circuit of claim 4 , wherein the first current signal is stored by a capacitor coupled to the gate terminals of the plurality of gated conductors.

6. The circuit of claim 5 , wherein when the first current signal is generated, the plurality of switches are turned on so as to cause the first current signal to be distributed by the plurality of gated conductors.

7. The circuit of claim 4 , wherein the gate terminals of the plurality of gated conductors are electrically coupled to an inverting input terminal of the comparator, and the resistor is electrically coupled to a non-inverting input terminal of the comparator.

8. The circuit of claim 7 , wherein when the second current signal is generated, the control circuit is configured to iteratively toggle one of the plurality of switches to deactivate the respective gated conductor until the comparator outputs a logical low value.

9. The circuit of claim 8 , wherein when the comparator outputs the logical low value, the control circuit estimates the reading of the monitored temperature based on toggled behaviors of the plurality of switches.

10. The circuit of claim 1 , wherein each gated conductor includes a p-type metal-oxide-semiconductor (PMOS) transistor.

11. A thermometer circuit configured to estimate a monitored temperature, comprising:
a magnetic tunnel junction (MTJ) cell presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the MTJ cell when it presents the first resistance value and a second current signal is conducted across the MTJ cell when it presents the second resistance value;
a plurality of gated conductors coupled to the MTJ cell; and
a control circuit, coupled to the MTJ cell and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature, wherein when the first current signal is generated, gate terminals of the plurality of gated conductors are electrically coupled to the MTJ cell and when the second current signal is generated, the gate terminals of the plurality of gated conductors are electrically decoupled from the MTJ cell.

12. The circuit of claim 11 , wherein the MTJ cell presents the first resistance value when the MTJ cell is in a parallel state, and the MTJ cell presents the second resistance value when the MTJ cell is in an anti-parallel state.

13. The circuit of claim 11 , further comprising:
a comparator coupled to the plurality of gated conductors and the MTJ cell; and
a plurality of switches, wherein each switch is coupled between the MTJ cell and a respective gated conductor, and wherein each switch is turned off to deactivate the respective gated conductor.

14. The circuit of claim 13 , wherein the first current signal is stored by a capacitor coupled to the gate terminals of the plurality of gated conductors.

15. The circuit of claim 14 , wherein when the first current signal is generated, the plurality of switches are turned on so as to cause the first current signal to be distributed by the plurality of gated conductors.

16. The circuit of claim 13 , wherein the gate terminals of the plurality of gated conductors are electrically coupled to an inverting input terminal of the comparator, and the MTJ cell is electrically coupled to a non-inverting input terminal of the comparator.

17. The circuit of claim 16 , wherein when the second current signal is generated, the control circuit is configured to iteratively toggle one of the plurality of switches to deactivate the respective gated conductor until the comparator outputs a logical low value.

18. A method for estimating a monitored temperature, comprising:
providing a first current signal, wherein the first current signal is conducted across a magnetic tunnel junction (MTJ) cell when it presents a temperature-independent resistance value, wherein when the first current signal is provided, gate terminals of the plurality of gated conductors are electrically coupled to the MTJ cell;
generating a first temperature code by turning on a plurality of coding switches configured to electrically couple and decouple respective ones of the plurality of gated conductors to the MTJ cell, wherein the first temperature code reflects the first current signal;
providing a second current signal, wherein the second current signal is conducted across the MTJ cell when it presents a temperature-dependent resistance value, wherein when the second current signal is provided, the gate terminals of the plurality of gated conductors are electrically decoupled from the MTJ cell;
comparing the first and second current signals by iteratively turning off one of the plurality of coding switches thereby generating a second temperature code, wherein the second temperature code reflects the second current signal; and
estimating the monitored temperature based on the second temperature code.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Shih-Lien Linus
• Lee Chia-Fu
• Shih Yi-Chun
• Chou Chung-Cheng
• Chih Yu-Der

Classifications

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title

• G01K7/16 Primary

  using resistive elements · CPC title