System and method for bit processing in a central network component

Patent metadata

Field	Value
Publication number	US-10284247-B2
Application number	US-201313913971-A
Country	US
Kind code	B2
Filing date	Jun 10, 2013
Priority date	Jun 10, 2013
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described.

First claim

What is claimed is:

1. A FlexRay-compatible central bus guardian (CBG) for facilitating communication among communication nodes that are connected to each other only through the FlexRay-compatible CBG, the FlexRay-compatible CBG comprising:
a bit oversampling module configured to oversample a plurality of bits received from a first communication node of the communication nodes that is directly connected to the FlexRay-compatible CBG with an oversampling factor to generate oversampled bit streams, wherein the oversample factor is a positive integer that is greater than or equal to sixteen and is agreed by the first communication node and the FlexRay-compatible CBG;
a bit majority voting module configured to perform majority voting to the oversampled bit streams using a slide window having three samples;
a strobing time point selection module configured to select time points in the oversampled bit streams after the majority voting, wherein the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, wherein the strobing time point selection module is further configured to select each time point in a respective oversampled bit stream of the oversampled bit streams when a sample counter within the FlexRay-compatible CBG is greater than or equal to a sum of a half of the oversampling factor and three, wherein the strobing time point selection module includes a sample clock adjustment module configured to adjust the sample counter within the FlexRay-compatible CBG that is used for selecting the time points, wherein the adjustment is performed to account for discrepancies due to a clock deviation between the first communication node and the FlexRay-compatible CBG, wherein the sample clock adjustment module is further configured to reset the sample counter within the FlexRay-compatible CBG to one in response to a rising synchronization edge that is known to the FlexRay-compatible CBG, wherein a fixed number of bits between which the rising synchronization edge is transmitted is agreed by the first communication node and the FlexRay-compatible CBG, and wherein the strobing time point selection module is further configured to select a first time point in the oversampled bit streams before the rising synchronization edge and a second time point in the oversampled bit streams after the rising synchronization edge such that the time difference between the first and second time points is equal to a fixed number of sample clocks when the length of the oversampled bit streams are different; and
a bit outputting module configured to output delayed versions of the inner samples to a second communication node of the communication nodes that is directly connected to the FlexRay-compatible CBG between the time points.

2. The FlexRay-compatible CBG of claim 1 , wherein the bit outputting module is further configured to output one of the inner samples out of the FlexRay-compatible CBG between a corresponding time point of the time points and a subsequent time point of the time points.

3. The FlexRay-compatible CBG of claim 1 , wherein the bit outputting module is further configured to, from one of the time points, keep a corresponding one of the inner samples as the output bit of the FlexRay-compatible CBG until a next time point.

4. The FlexRay-compatible CBG of claim 1 , wherein the strobing time point selection module is further configured to: increase the sample counter for each bit in one of the oversampled bit streams; and select a time point in the one of the oversampled bit streams when the sample counter is greater than or equal to the sum of a half of the oversampling factor and three.

5. The FlexRay-compatible CBG of claim 1 , wherein the bit oversampling module is further configured to oversample a first received bit to generate a first oversampled bit stream and oversample a second received bit to generate a second oversampled bit stream, wherein the strobing time point selection module is further configured to select a first time point that corresponds to an inner sample in the first oversampled bit stream and select a second time point that corresponds to an inner sample in the second oversampled bit stream, wherein the bit outputting module is further configured to output the inner sample in the first oversampled bit stream to the second communication node between the first time point and the second time point.

6. The FlexRay-compatible CBG of claim 1 , wherein the plurality of bits includes a bit pattern that is known to the FlexRay-compatible CBG, and wherein the time point selection module is further configured to adjust the sample counter in response to the bit pattern.

7. The FlexRay-compatible CBG of claim 1 , wherein the time point selection module is further configured to select the time points in the oversampled bit streams such that time differences between adjacent time points are equivalent when the length of the bits received from the first communication node are different.

8. The FlexRay-compatible CBG of claim 1 , wherein the sample clock adjustment module is further configured to increase the sample counter within the FlexRay-compatible CBG to two with an arrival of a next voted sample.

9. A FlexRay-compatible central bus guardian (CBG) for facilitating communication among FlexRay-compatible communication nodes in an automobile system that are connected to each other only through the FlexRay-compatible CBG, the FlexRay-compatible CBG comprising:
a bit oversampling module configured to oversample a plurality of bits received from a first FlexRay-compatible communication node of the FlexRay-compatible communication nodes that is directly connected to the FlexRay-compatible CBG with an oversampling factor to generate oversampled bit streams, wherein the oversample factor is a positive integer that is greater than or equal to sixteen and is agreed by the first communication node and the FlexRay-compatible CBG;
a bit majority voting module configured to perform majority voting to the oversampled bit streams using a slide window having three samples;
a strobing time point selection module configured to select time points in the oversampled bit streams after the majority voting, wherein the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, wherein the strobing time point selection module is further configured to select each time point in a respective oversampled bit stream of the oversampled bit streams when a sample counter within the FlexRay-compatible CBG is greater than or equal to a sum of a half of the oversampling factor and three, wherein the strobing time point selection module includes a sample clock adjustment module configured to adjust the sample counter within the FlexRay-compatible CBG that is used for selecting the time points, wherein the adjustment is performed to account for discrepancies due to a clock deviation between the first communication node and the FlexRay-compatible CBG, wherein the sample clock adjustment module is further configured to reset the sample counter within the FlexRay-compatible CBG to one in response to a rising synchronization edge that is known to the FlexRay-compatible CBG, wherein a fixed number of bits between which the rising synchronization edge is transmitted is agreed by the first communication node and the FlexRay-compatible CBG, and wherein the strobing time point selection module is further configured to select a first time point in the oversampled bit streams before the rising synchronization edge and a second time point in the oversampled bit streams after the rising synchronization edge such that the time difference between the first and second time points is equal to a fixed number

Assignees

• Nxp Bv

Inventors

• Deb Abhijit Kumar
• Vermeulen Hubertus Gerardus Hendrikus
• Pandey Sujan

Classifications

• H04L12/40013 Primary

  Details regarding a bus controller · CPC title

• H04B1/3822 Primary

  specially adapted for use in vehicles (H04B1/3827 takes precedence) · CPC title