Pure memristive logic gate

Patent metadata

Field	Value
Publication number	US-10284203-B2
Application number	US-201715622090-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Jun 14, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

First claim

We claim:

1. A device that comprises a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that (a) is coupled to the at least one input memristive device, and (b) differs from the at least one input memristive device; wherein the pure memristive logic gate is controlled by a single control voltage; and wherein the pure memristive logic gate is arranged to operate in a first phase in which the output memristive device is initialized to a known value and a second phase in which the single control voltage is applied to one or more input memristive devices of the at least one input memristive device thereby affecting state of the output memristor that is an output of the pure memristive logic gate.

2. The device according to claim 1 wherein the polarity of the output memristive device is a same to a polarity of each input memristive device.

3. The device according to claim 1 wherein the pure memristive logic gate is integrated with a memristive device memory array.

4. The device according to claim 1 wherein the pure memristive logic gate is integrated with a memristive device crossbar that functions as a memristive memory array.

5. The device according to claim 4 wherein the pure memristive logic gate is a NOR logic gate.

6. The device according to claim 4 wherein the pure memristive logic gate is a NOT logic gate.

7. The device according to claim 1 wherein the pure memristive logic gate is a NOT logic gate that consists essentially of a single input memristive device that is serially coupled between a supplier of the single control voltage and the output memristive device.

8. The device according to claim 1 wherein the pure memristive logic gate is a NOR logic gate that consists essentially of multiple input memristive devices that are coupled in parallel to each other between a supplier of the single control voltage and the output memristive device; wherein a polarity of the multiple input memristive devices is opposite to a polarity of the output memristive device.

9. The device according to claim 1 wherein the pure memristive logic gate is a NAND logic gate that consists essentially of multiple input memristive devices that are coupled in serial to each other between a supplier of the single control voltage and the output memristive device, wherein a polarity of the multiple input memristive devices is opposite to a polarity of the output memristive device.

10. The device according to claim 1 wherein the pure memristive logic gate is an AND logic gate that consists essentially of multiple input memristive devices that are coupled in serial to each other between a supplier of the single control voltage and the output memristive device, wherein a polarity of the multiple input memristive devices is a same as a polarity of the output memristive device.

11. The device according to claim 1 wherein the pure memristive logic gate is an OR logic gate that consists essentially of multiple input memristive devices that are coupled in parallel to each other between a supplier of the single control voltage and the output memristive device; wherein a polarity of the multiple input memristive devices is a same as a polarity of the output memristive device.

12. The device according to claim 1 wherein the at least one input memristive device is a first input memristive device and a second input memristive device that are coupled in parallel to each other; wherein the output memristive device (a) is serially coupled to the first and second input memristive devices, (b) differs from the first and second input memristive devices, and (c) has a reverse polarity than the first and second input memristive devices; wherein the pure memristive logic gate is integrated with a memristive device crossbar that functions as a memristive memory array; and wherein the pure memristive logic gate is a NOR logic gate.

13. The device according to claim 12 wherein the first input memristive device is connected between a first row of the memristive device crossbar and a first column of the memristive device crossbar; wherein the second input memristive device is connected between a second row of the memristive device crossbar and the first column of the memristive device crossbar; and wherein the output memristive device is connected between a third row of the memristive device crossbar and the first column of the memristive device crossbar.

14. The device according to claim 12 wherein a state of the pure memristive logic gate is represented only as resistance.

15. A device that comprises a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that (a) is coupled to the at least one input memristive device, and (b) differs from the at least one input memristive device; wherein the pure memristive device is controlled by a single control voltage; wherein a polarity of the output memristive device is reverse to a polarity of each input memristive device.

16. A method for performing a logic operation, the method comprises:
initializing an output memristive device of a pure memristive logic gate to a known value; and
applying a single control voltage to one or more input memristive device of at least one input memristive device of the pure memristive logic gate thereby affecting state of an output memristor that is an output of the pure memristive logic gate.

17. The method according to claim 16 wherein a polarity of the output memristive device is reverse to a polarity of each input memristive device.

18. The method according to claim 16 wherein the pure memristive logic gate is integrated with a memristive device memory array.

19. The device according to claim 16 wherein the pure memristive logic gate is integrated with a memristive device crossbar that functions as a memristive memory array.

Assignees

• Technion Res & Development Found Ltd

Inventors

• Kvatinsky Shahar
• Belousov Dmitry
• Liman Slavik
• Wald Nimrod
• Satat Guy

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title