Protective circuit enabling different bias levels responsive to event faults

Patent metadata

Field	Value
Publication number	US-10284191-B2
Application number	US-201615225507-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Jul 31, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.

First claim

The invention claimed is:

1. A circuit protective system, comprising:
a gate output adapted to be coupled to a gate of a transistor;
a sense input adapted to be coupled to the transistor and sense an operational parameter associated with the transistor;
detection circuitry coupled to the sense input and providing an event fault indicator signal on an event output if a sensed operational parameter violates a condition; and
protective circuitry coupled to the event output and the gate output, the protective circuitry applying a disabling signal on the gate output in response to the event fault indicator signal and subsequently selectively applying an enabling bias to the gate output, the enabling bias selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.

2. The circuit protective system of claim 1 in which the operational parameter associated with the transistor includes transistor current.

3. The circuit protective system of claim 1 in which the operational parameter associated with the transistor includes transistor temperature.

4. The circuit protective system of claim 1 in which the operational parameter associated with the transistor includes transistor temperature exceeding a threshold beyond a period of time.

5. The circuit protective system of claim 1 in which the operational parameter associated with the transistor includes transistor energy.

6. The circuit protective system of claim 1 in which the detection circuitry provides an event fault indicator signal if a value of the operation parameter exceeds a threshold.

7. The circuit protective system of claim 6 :
in which the protective circuitry applies a first bias level to the gate output for nominal bias and the condition includes a current limit at a first level; and
in which the protective circuitry applies a second bias level to the gate output for foldback bias, less than the first bias, and the condition includes a current limit at a second level less than the current limit at a first level.

8. The circuit protective system of claim 1 :
in which the operational parameter associated with the transistor includes transistor energy; and
in which the detection circuitry provides an event fault indicator signal if the disabling of the transistor exceeds a transistor energy threshold.

9. The circuit protective system of claim 1 in which the sense input senses a plurality of operational parameters associated with the transistor and the detection circuitry provides an event fault indicator signal if any operational parameter violates a respective condition.

10. The circuit protective system of claim 9 in which the plurality of operational parameters associated with the transistor includes transistor current, transistor temperature, and transistor energy.

11. The circuit protective system of claim 1 in which the detection circuitry includes a state machine.

12. The circuit protective system of claim 1 and further including the transistor.

13. The circuit protective system of claim 12 in which the output is coupled to a gate of the transistor.

14. The circuit protective system of claim 1 in which a first enabling bias level is a nominal bias level and a second enabling bias level is less than the nominal bias level.

15. The circuit protective system of claim 1 in which a first enabling bias level is a nominal bias level and a second enabling bias level is approximately fifty percent of the nominal bias level.

16. The circuit protective system of claim 1 in which the enabling bias is selected in response to at least three successive event fault indications from the detection circuitry.

17. The circuit protective system of claim 1 :
in which a first bias level, in the at least two different bias levels, includes a nominal bias that enables the transistor to provide a first level of current; and
in which a second bias level, in the at least two different bias levels, includes a bias that enables the transistor to provide a second level of current, less than the first level of current.

18. The circuit protective system of claim 17 in which the second level of current is approximately fifty percent of the first level of current.

19. The circuit protective system of claim 17 in which the second bias level is selected in response to at least three successive event fault indications from the detection circuitry.

20. The circuit protective system of claim 17 in which, after selecting the second bias level, the protective circuitry selects the first bias level following a time period in which the detection circuitry does not provide an event fault indicator.

21. The circuit protective system of claim 20 in which the time period includes 100 microseconds.

22. A circuit protective system, comprising:
a gate output adapted to be coupled to a gate of a transistor;
a sense input adapted to be coupled to the transistor and couple a transistor operational parameter to detection circuitry, the detection circuitry providing an event fault indicator signal if the operational parameter violates a condition; and
protective circuitry coupled to the event fault indicator signal, the protective circuitry applying a disable signal on the gate output in response to the event fault indicator signal and subsequently selectively applying an enabling bias to the gate output, the enabling bias selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.

Assignees

• Texas Instruments Inc

Inventors

• Rahman Md Abidur
• Quirk Adam
• Nortman Stephen
• Aras Sualp

Classifications

• H03K2017/0806

  against excessive temperature · CPC title

• H02H5/041

  additionally responsive to excess current (H02H5/048 takes precedence) · CPC title

• H02H3/00

  Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection (specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems H02H7/00; systems for change-over to standby supply H02J9/00 ){; integrated protection (for motors H02H7/0822)} · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H02H3/06

  with automatic reconnection · CPC title