LNA with programmable linearity

Patent metadata

Field	Value
Publication number	US-10284151-B2
Application number	US-201815895863-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Sep 21, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

First claim

What is claimed is:

1. An amplifier comprising:
(a) a plurality of amplifier branches, at least one of which includes a driver field effect transistor (FET) having a drain, source and gate, and a corresponding cascode FET having a drain, source and gate, the drain of the driver FET coupled to the source of the corresponding cascode FET, the drain of each cascode FET coupled together;
(b) a plurality of branch control switches, each branch control switch associated with one of the amplifier branches and coupled to the gate of the cascode FET within the corresponding amplifier branch;
(c) a load inductance having a first and second terminal, the first terminal coupled to the drains of the cascode FETs and the second terminal coupled to a voltage supply;
(d) an output capacitor having a first and second terminal, the first terminal coupled to the drains of the cascode FETs and the second terminal coupled to an amplifier output;
(e) a plurality of gain control compensation capacitors, each having a first and second terminal, the first terminal of each gain control compensation capacitor coupled to the drains of the cascode FETs;
(f) a plurality of gain control compensation switches, each gain control compensation switch corresponding to one of the plurality of gain control compensation capacitors and having a first and second terminal, the first terminal coupled to the second terminal of the corresponding gain control compensation capacitor and the second terminal of each of the gain control compensation switches coupled to the amplifier output to place the corresponding gain control compensation capacitor in parallel with an output capacitor when the corresponding gain control compensation switch is closed.

2. The amplifier of claim 1 , further comprising a plurality of selectable gate to source compensation (GSC) capacitors, each GSC coupled between the gate and the source of a corresponding one of the driver FETs.

3. The amplifier of claim 2 , further comprising a plurality of GSC switches, each coupled to a corresponding one of the plurality of GSC capacitors and associated with a corresponding one of the amplifier branches.

4. The amplifier of claim 3 , wherein the amplifier has an input impedance and wherein turning on unique combinations of amplifier branches corresponds to unique gain modes and wherein combinations of the GSC capacitors are tuned to mitigate changes between the input impedance in each of the possible gain modes.

5. The amplifier of claim 3 , further comprising a plurality of selectable degeneration capacitors coupled to the sources of the driver FETs.

6. The amplifier of claim 5 , further comprising a plurality of degeneration switches, each degeneration switch coupled to a corresponding one of the degeneration capacitors.

7. The amplifier of claim 6 , wherein the amplifier has an input impedance and wherein turning on unique combinations of amplifier branches corresponds to unique gain modes and wherein combinations of the degeneration capacitors are tuned to reduce input impedance variation between each of the possible gain modes.

8. The amplifier of claim 1 , further including a plurality of output impedance compensation (OIC) capacitors, each of which can be placed in parallel with the load inductance.

9. The amplifier of claim 8 , further including a plurality of OIC switches, each OIC switch associated with one of the OIC capacitors such that when closed the OIC switch places the OIC capacitor in parallel with the load inductance.

10. The amplifier of claim 9 , wherein each of the OIC switches is associated with one of the amplifier branches, such that when a signal turns off the amplifier branch, the associated OIC switch is closed.

11. The amplifier of claim 10 , wherein the capacitance of the OIC capacitor associated with the each OIC switch is selected such that closing the associated OIC switch improves the output impedance mismatch when the associated driver FET is turned off.

12. The amplifier of claim 3 , wherein the GSC capacitors are post fabrication variable.

13. The amplifier of claim 12 , wherein the GSC capacitors are laser trimmed after fabrication to adjust the capacitance to a desired capacitance after fabrication is complete.

Assignees

• Psemi Corp

Inventors

• Noori Hossein
• Cheng Chih-Chieh

Classifications

• H03F2200/492

  A coil being added in the source circuit of a transistor amplifier stage as degenerating element · CPC title

• H03F2200/75

  the amplifier stage being a common source configuration MOSFET · CPC title

• F23C2201/301

  with different fuels in stages · CPC title

• H03G1/0094

  using switched capacitors · CPC title

• H03F2200/399

  A parallel resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage · CPC title