Motor diving circuit

US10284124B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10284124-B2
Application numberUS-201715663666-A
CountryUS
Kind codeB2
Filing dateJul 28, 2017
Priority dateMar 17, 2017
Publication dateMay 7, 2019
Grant dateMay 7, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A motor driving circuit for receiving a control signal to output at least one output current for driving a motor is provided. The motor driving circuit includes an input module, a gain module, an output module, a first slew rate limiting module, and a second slew rate limiting module. The first slew rate limiting module has a first limiting parameter. The second slew rate includes a second limiting parameter. An output current is outputted by the output terminal. When a rising slew rate of the output current is less than a first slew rate value, the first slew rate limiting module does not operate. When the rising slew rate of the output current is greater than the first slew rate value, the motor driving circuit limits the rising slew rate of the output current based on the first limiting parameter of the first slew rate limiting module.

First claim

Opening claim text (preview).

What is claimed is: 1. A motor driving circuit for receiving a control signal to output at least one output current for driving a motor, the motor driving circuit comprising: an input module for receiving the control signal and transforming the control signal as an input signal; a gain module electrically connected to the input module for receiving and amplifying the input signal; an output module electrically connected to the gain module, wherein the output module includes an output terminal; the output module including: a first output switch including a first terminal, a second terminal and a third terminal, wherein the second terminal of the first output switch is used for receiving a first output control signal of the gain module; a second output switch including a first terminal, a second terminal and a third terminal, wherein the second terminal of the second output switch is used for receiving a second output control signal of the gain module, and the first terminal of the second output switch is electrically connected to the third terminal of the first output switch; a first slew rate limiting module including a first limiting terminal and a second limiting terminal, the first limiting terminal electrically connected to the output terminal of the output module, and the second limiting terminal electrically connected to the second terminal of the first output switch, wherein the first slew rate limiting module has a first limiting parameter; and a second slew rate limiting module including a first limiting terminal and a second limiting terminal, the first limiting terminal electrically connected to the output terminal of the output module, and the second limiting terminal electrically connected to the second terminal of the second output switch, wherein the second slew rate includes a second limiting parameter; wherein an output current is outputted by the output terminal of the output module; when a rising slew rate of the output current is less than a first slew rate value, the first slew rate limiting module does not operate; when the rising slew rate of the output current is greater than the first slew rate value, the motor driving circuit limits the rising slew rate of the output current based on the first limiting parameter of the first slew rate limiting module; wherein the first slew rate limiting module comprises: a first current mirror unit including: a first current mirror switch including a first terminal, a second terminal and a third terminal, the first terminal of the first current mirror switch electrically connected to a first reference voltage; and a second current mirror switch including a first terminal, a second terminal and a third terminal, the first terminal of the second current mirror switch electrically connected to the first reference voltage; and a first limiting unit including: a first limiting capacitance including a first terminal and a second terminal; a first limiting switch including a first terminal, a second terminal and a third terminal; and a second limiting switch including a first terminal, a second terminal and a third terminal, wherein the third terminal of the first limiting switch and the third terminal of the second limiting switch are electrically connected a second reference voltage; and wherein the second terminal of the first current mirror switch is electrically connected to the second terminal of the second current mirror switch and the third terminal of the second current mirror switch, the third terminal of the first current mirror switch is electrically connected to the first limiting terminal of the first slew rate limiting module, the third terminal of the second current mirror switch is electrically connected to the first terminal of the second limiting switch, the first terminal of the first limiting switch is electrically connected to the second terminal of the second limiting switch, the second terminal of the first limiting switch is electrically connected to a first bias voltage, the first terminal of the first limiting switch is electrically connected to the second terminal of the first limiting capacitance, and the first terminal of the first limiting capacitance is electrically connected to the second limiting terminal of the first slew rate limiting module. 2. The motor driving circuit of claim 1 , wherein when a falling slew rate of the output current is less than a second slew rate value, the second slew rate limiting module does not operate; when the falling slew rate of the output current is greater than the second slew rate value, the motor driving circuit limits the falling slew rate of the output current based on the second limiting parameter of the second slew rate limiting module. 3. The motor driving circuit of claim 1 , wherein the first terminal of the first output switch is electrically connected to a third reference voltage, the second terminal of the first output switch is electrically connected to the gain module, the third terminal of the first output switch is electrically connected to the first terminal of the second output switch and the output terminal of the output module, the second terminal of the second output switch is electrically connected to the gain module, and the third terminal of the second output switch is electrically connected to a fourth reference voltage. 4. The motor driving circuit of claim 1 , wherein the second slew rate limiting module comprises: a second current mirror unit including: a first current mirror switch including a first terminal, a second terminal and a third terminal, the third terminal of the first current mirror switch electrically connected to a sixth reference voltage; and a second current mirror switch including a first terminal, a second terminal and a third terminal, the third terminal of the second current mirror switch electrically connected to the sixth reference voltage; and a second limiting unit including: a second limiting capacitance including a first terminal and a second terminal; a first limiting switch including a first terminal, a second terminal and a third terminal; and a second limiting switch including a first terminal, a second terminal and a third terminal, wherein the first terminal of the first limiting switch and the first terminal of the second limiting switch are electrically connected to a fifth reference voltage; wherein the second terminal of the first current mirror switch of the second current mirror unit is electrically connected to the second terminal of the second current mirror switch of the second current mirror unit and the first terminal of the second current mirror switch of the second current mirror unit, the first terminal of the first current mirror switch of the second current mirror unit is electrically connected to the first limiting terminal of the second slew rate limiting module, the first terminal of the second current mirror switch of the second current mirror unit is electrically connected to the third terminal of the second limiting switch of the second limiting unit, the third terminal of the first limiting switch of the second limiting unit is electrically connected to the second terminal of the second limiting switch, the second terminal of the first limiting switch of the second limiting unit is electrically connected to a second bias voltage, the third terminal of the first limiting switch of the second limiting unit is electrically connected to the first terminal of the second limiting capacitance, and the second terminal of the second limiting capacitance is electrically connected to the second limiting terminal of the second slew rate limiting module. 5. The motor driving circuit of claim 1 , wherein the first limiting parameter is determined according to a first limiting current flowing through the firs

Assignees

Inventors

Classifications

  • Arrangements for starting (H02P6/08 takes precedence) · CPC title

  • in field-effect transistor switches · CPC title

  • Electricity · mapped topic

  • in a bridge configuration · CPC title

  • H02P7/28Primary

    using semiconductor devices · CPC title

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Frequently asked questions

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What does patent US10284124B2 cover?
A motor driving circuit for receiving a control signal to output at least one output current for driving a motor is provided. The motor driving circuit includes an input module, a gain module, an output module, a first slew rate limiting module, and a second slew rate limiting module. The first slew rate limiting module has a first limiting parameter. The second slew rate includes a second limi…
Who is the assignee on this patent?
Anpec Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H02P7/28. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).