Scalable process for the formation of self aligned, planar electrodes for devices employing one or two dimensional lattice structures

Patent metadata

Field	Value
Publication number	US-10283629-B2
Application number	US-201615298771-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Oct 21, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A method of forming an electrical device that includes forming a gate dielectric layer over a gate electrode, forming source and drain electrodes on opposing sides of the gate electrode, wherein one end of the source and drain electrodes provides a coplanar surface with the gate dielectric, and positioning a 1D or 2D nanoscale material on the coplanar surface to provide the channel region of the electrical device.

First claim

What is claimed is:

1. An electrical device comprising:
a planar interface provided by a top surface of a gate dielectric, a top surface of a source electrode and a top surface of a drain electrode that are arranged in coplanar relationship with the gate dielectric electrically isolating the source electrode and the drain electrode from a substrate;
a one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof providing the channel region of the electrical device that is present on the planar interface and is in direct contact with the top surface of the gate dielectric; and
a gate electrode in-between the substrate and the gate dielectric, with the source electrode in direct contact with a first sidewall portion of the gate dielectric that is present on a first sidewall of the gate electrode.

2. The electrical device of claim 1 , wherein the one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof is selected from the group consisting of carbon nanotubes, graphene, transition metal dichalcogenides, black phosphorus and a combination thereof.

3. The electrical device of claim 1 , wherein the source electrode and the drain electrode are adjacent to the gate electrode.

4. The electrical device of claim 3 , wherein the gate electrode is comprised of tungsten (W), titanium (Ti), palladium (Pd), gold (Au), chromium (Cr), or a combinations thereof.

5. The electrical device of claim 3 , wherein at least one of the source electrode and the drain electrode are comprised of tungsten (W), titanium (Ti), palladium (Pd), gold (Au), chromium (Cr), or a combinations thereof.

6. The electrical device of claim 3 , wherein said gate dielectric comprises silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride, HfO 2 , ZrO 2 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , hafnium silicon oxide, hafnium silicon oxynitride, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, nitrided hafnium silicate (HfSiON), lanthanum oxide (La 3 O 2 ), zirconium silicate (ZrSiO x ) or a combination thereof.

7. An electrical device comprising:
a planar interface provided by a top surface of a gate dielectric, a top surface of a source electrode and a top surface of a drain electrode that are arranged in coplanar relationship with the gate dielectric electrically isolating the source electrode and the drain electrode from a substrate;
a one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof providing the channel region of the electrical device that is present on the planar interface and is in direct contact with the top surface of the gate dielectric; and
a gate electrode in-between the substrate and the gate dielectric, with the drain electrode in direct contact with a second sidewall portion of the gate dielectric that is present on a second sidewall of the gate electrode.

8. The electrical device of claim 7 , wherein the one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof is selected from the group consisting of carbon nanotubes, graphene, transition metal dichalcogenides, black phosphorus and a combination thereof.

9. The electrical device of claim 7 , wherein the source electrode and the drain electrode are adjacent to the gate electrode.

10. The electrical device of claim 9 , wherein the gate electrode is comprised of tungsten (W), titanium (Ti), palladium (Pd), gold (Au), chromium (Cr), or a combinations thereof.

11. The electrical device of claim 7 , wherein at least one of the source electrode and the drain electrode are comprised of tungsten (W), titanium (Ti), palladium (Pd), gold (Au), chromium (Cr), or a combinations thereof.

12. An electrical device comprising:
a planar interface provided by a top surface of a gate dielectric, a top surface of a source electrode and a top surface of a drain electrode that are arranged in coplanar relationship with the gate dielectric electrically isolating the source electrode and the drain electrode from a substrate;
a one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof providing the channel region of the electrical device that is present on the planar interface and is in direct contact with the top surface of the gate dielectric, wherein the 1D or 2D nanoscale material is selected from the group consisting of carbon nanotubes, graphene, transition metal dichalcogenides and a combination thereof; and
a gate electrode in-between the substrate and the gate dielectric, with the source electrode in direct contact with a first sidewall portion of the gate dielectric that is present on a first sidewall of the gate electrode, and the drain electrode in direct contact with a second sidewall portion of the gate dielectric that is present on a second sidewall of the gate electrode.

13. The electrical device of claim 12 , wherein said gate dielectric comprises silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride, HfO 2 , ZrO 2 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , hafnium silicon oxide, hafnium silicon oxynitride, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, nitrided hafnium silicate (HfSiON), lanthanum oxide (La 3 O 2 ), zirconium silicate (ZrSiO x ) or a combination thereof.

Assignees

• IBM

Inventors

• Engel Michael
• Steiner Mathias B

Classifications

• H01L29/1606

  Electricity · mapped topic

• H01L51/0545

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic

• H01L29/66969 Primary

  Electricity · mapped topic

• H01L29/66045

  Electricity · mapped topic