Low resistance contacts to source or drain region of transistor

Patent metadata

Field	Value
Publication number	US-10283608-B2
Application number	US-201715461634-A
Country	US
Kind code	B2
Filing date	Mar 17, 2017
Priority date	Mar 17, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a gate structure on a channel portion of a semiconductor fin, wherein a source region and a drain region are present on opposing sides of the channel portion;
forming an epitaxial layer over the source region and the drain region: forming a dielectric layer over the gate structure:
forming a trench extending through the dielectric layer to an exposed surface of at least one of the source region or the drain region;
forming a single metal liner over sidewalls of the trench and over the at least one of the source region or the drain region, such that the single metal liner continuously contacts each of the sidewalls of the trench and one of the source region or the drain region, wherein the single metal liner includes a metal silicide-forming metal; and
forming a conductive fill material over the single metal liner and filling the trench, such that the conductive fill material continuously contacts the single metal liner, wherein the single metal liner physically separates the conductive fill material from the sidewalls of the trench and one of the source region or the drain region, and wherein the conductive fill material comprises a platinum group metal.

2. The method of claim 1 , wherein the single metal liner comprises titanium and the conductive fill material comprises ruthenium.

3. The method of claim 1 , wherein forming the single metal liner comprises physical vapor deposition.

4. The method of claim 1 , wherein the single metal liner is formed directly over the at least one of the source region or the drain region.

5. The method of claim 1 , wherein a ratio of a thickness of the single metal liner over the at least one of the source region or the drain region to a thickness of the single metal liner over the sidewalls of the trench is from 2 to 10.

6. A method of forming a semiconductor device, comprising:
forming a gate structure on a channel portion of a semiconductor fin, wherein a source region and a drain region are present on opposing sides of the channel portion;
forming an epitaxial layer over the source region and the drain region: forming a dielectric layer over the gate structure:
forming a trench extending through the dielectric layer to an exposed surface of at least one of the source region or the drain region;
forming a metal liner over sidewalls of the trench and over the at least one of the source region or the drain region, such that the metal liner continuously contacts each of the sidewalls of the trench and the source region or the drain region, wherein the metal liner includes a metal silicide-forming metal;
forming a barrier layer on exposed surfaces of the metal liner with a downward directional deposition, wherein the barrier layer includes a lower portion having a first thickness and an upper portion having a second thickness, the second thickness being less than the first thickness; and
forming a conductive fill material over the metal liner and filling the trench, such that the conductive fill material continuously contacts the barrier layer, wherein the barrier layer physically separates the conductive fill material from the metal liner, and wherein the conductive fill material comprises a platinum group metal.

7. The method of claim 6 , wherein the barrier layer comprises titanium nitride (TiN).

8. The method of claim 7 , wherein the metal liner comprises titanium (Ti) and the conductive fill material comprises ruthenium (Ru).

9. The method of claim 6 , wherein forming the metal liner comprises physical vapor deposition.

10. The method of claim 6 , wherein the metal liner is formed directly over one of the source region or the drain region, and wherein the metal liner physically separates the barrier layer from the source region or the drain region.

11. The method of claim 6 , wherein a ratio of the first thickness of the lower portion of the barrier layer to the thickness of the upper portion of the barrier layer is from approximately 2 to approximately 10.

Assignees

• Globalfoundries Inc

Inventors

• Zhang Xunyuan
• Mont Frank
• Raymond Mark
• Niu Chengyu

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title