Metal density distribution for double pattern lithography

Patent metadata

Field	Value
Publication number	US-10283437-B2
Application number	US-201213686184-A
Country	US
Kind code	B2
Filing date	Nov 27, 2012
Priority date	Nov 27, 2012
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

First claim

What is claimed is:

1. A method comprising:
decomposing an overall pattern into:
a first mask pattern that includes a power rail base pattern; and
a second mask pattern; and

generating, on the second mask pattern, a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern, the generating comprising:
selecting, for the power rail insert pattern, one or more inserts to be used to overlay the power rail base pattern of the first mask pattern; and
adding, to the second mask pattern, the one or more inserts in an arrangement in which the one or more inserts improve an exposure dose balance for corresponding regions of a power rail in a semiconductor wafer that is fabricated using the first mask pattern and the second mask pattern.

2. The method of claim 1 , wherein decomposing the overall pattern includes decomposing the power rail base pattern into an area of a first power rail on the first mask pattern and decomposing the power rail base pattern into an area of a second power rail on the first mask pattern, and
wherein generating the power rail insert pattern includes generating a first insert pattern at the area of the first power rail on the second mask pattern and generating a second insert pattern at the area of the second power rail on the second mask pattern.

3. The method of claim 1 , further including selecting a dimension of at least one of the one or more inserts of the power rail insert pattern based on a distance between the power rail base pattern and a feature of a cell that is patterned in the second mask pattern.

4. The method of claim 1 , wherein decomposing the overall pattern includes decomposing interconnect patterns of the overall pattern between the first mask pattern and the second mask pattern, and
wherein generating the power rail insert pattern includes generating the power rail insert pattern based on a distance between the power rail base pattern and a nearest one of the interconnect patterns on the second mask pattern.

5. The method of claim 1 , further comprising:
providing the overall pattern, the overall pattern including a plurality of cell patterns that each include a portion of the power rail base pattern, and
wherein decomposing the overall pattern includes decomposing the overall pattern into the power rail base pattern that is partially disposed in each of the cell patterns, and
wherein generating the power rail insert pattern includes generating two or more inserts that are separated along a longitudinal direction of the power rail base pattern.

6. The method of claim 5 , further including selecting a dimension of each of the two or more inserts based on a distance in a transverse direction between each of the two or more inserts and a nearest interconnect pattern on the second mask pattern that is aligned in the longitudinal direction with a respective insert of the two or more inserts whose dimension is to be selected.

7. The method of claim 1 , further including selecting a size of the power rail insert pattern based on an exposure dose skew between the first mask pattern and the second mask pattern.

8. The method of claim 1 , wherein generating the power rail insert pattern includes generating two or more inserts that are separated along a transverse direction of the power rail base pattern to conform to stitching rules of a lithographic process.

9. The method of claim 1 , further including creating a first photolithographic mask that includes the first mask pattern and creating a second photolithographic mask that includes the second mask pattern.

10. The method of claim 1 , further including fabricating a semiconductor device using a first photolithographic mask that includes the first mask pattern and a second photolithographic mask that includes the second mask pattern.

11. A method of fabricating a semiconductor device, comprising:
providing a semiconductor wafer;
providing a first photolithographic mask that includes a first image having a power rail base pattern;
transferring the first image onto the wafer;
providing a second photolithographic mask that includes a second image having a power rail insert pattern disposed to align within the power rail base pattern of the first photolithographic mask, the power rail insert pattern comprising one or more inserts to be used to overlay the power rail base pattern of the first image, the one or more inserts placed in the second image in an arrangement in which the one or more inserts improve an exposure dose balance for corresponding regions of a power rail in a semiconductor wafer that is fabricated using the first image and the second image;
transferring the second image onto the wafer;
etching a plurality of trenches in the wafer using the transferred first image and the transferred second image as an etch mask; and
depositing a conductive material in the trenches of the wafer to print the power rail.

12. The method of claim 11 , wherein providing the semiconductor wafer further includes providing the semiconductor wafer having an insulating layer and a hard mask layer disposed on the insulating layer; and wherein transferring the first image includes:
exposing the first image of the first photolithographic mask on a first photoresist disposed on the wafer;
developing the first photoresist to form a first etch mask that includes the power rail base pattern; and
etching the first image into the hard mask layer using the first etch mask.

13. The method of claim 12 , wherein transferring the second image includes:
exposing the second image of the second photolithographic mask on a second photoresist disposed on the wafer;
developing the second photoresist to form a second etch mask that includes the power rail insert pattern; and
etching the second image into the hard mask layer using the second etch mask.

14. The method of claim 13 , wherein etching the plurality of trenches in the wafer includes etching the insulating layer using the hard mask layer as a hard etch mask.

Assignees

• Advanced Micro Devices Inc

Inventors

• Schultz Richard T
• Rowhani Omid
• Tung Charles P

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H01L21/31144

  Electricity · mapped topic

• H01L2924/0001

  Electricity · mapped topic

• G03F7/0035

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title