Multilayer ceramic capacitor and method for producing the same

Patent metadata

Field	Value
Publication number	US-10283272-B2
Application number	US-201615163950-A
Country	US
Kind code	B2
Filing date	May 25, 2016
Priority date	Jun 5, 2015
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A multilayer ceramic capacitor having inner electrodes containing at least one metal selected from Cu, Ag, Pd, Pt, Rh, Ir, Ru, and Os in an amount of 0.1 atom % or more that is dissolved in Ni and Sn to form a solid solution. The percentage of Sn with respect to the total amount of Ni and Sn in near-surface regions each located at a depth of 2 nm from a surface of the inner electrode in contact with an adjacent ceramic dielectric layer is 1.4 or more atom %, and X−Y≥1.0, where X represents the atomic percentage of Sn in the near-surface regions and Y represents the atomic percentage of Sn in mid-thickness regions of the inner electrodes. A method for producing a multilayer ceramic capacitor includes annealing the ceramic multilayer body to increase, in the inner electrodes, the percentage of Sn in the near-surface regions.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a ceramic multilayer body including a stack of a plurality of ceramic dielectric layers and a plurality of inner electrodes arranged opposing each other with a respective ceramic dielectric layer of the plurality of ceramic dielectric layers interposed therebetween; and
outer electrodes disposed on an outer surface of the ceramic multilayer body, each outer electrode being in electrical connection with a respective set of inner electrodes of the plurality of inner electrodes,
the inner electrodes including a Ni—Sn-Metal A alloy, wherein the Metal A is at least one metal selected from the group consisting of Cu, Ag, Pd, Pt, Rh, Ir, Ru, and Os in an amount of 0.1 atom % or more,
a percentage of Sn with respect to a total amount of Ni and Sn in near-surface regions of the plurality of inner electrodes is 1.4 or more atom %, each of the near-surface regions being a region at a depth of within 2 nm from a surface in contact with an adjacent one of the respective ceramic dielectric layers, and
X−Y≥ 1.0

where X represents an atomic percentage of Sn in the near-surface regions and Y represents an atomic percentage of Sn in mid-thickness regions of the plurality of inner electrodes.

2. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of inner electrodes have a thickness defined as T, and each of the mid-thickness regions is located 0.2T or more inward from each surface of the plurality of inner electrodes in a thickness direction thereof.

3. The multilayer ceramic capacitor according to claim 1 , wherein the Ni—Sn-Metal A alloy contains a solid solution of Ni, Sn and the Metal A.

4. The multilayer ceramic capacitor according to claim 1 , wherein the plurality of inner electrodes contain a co-material.

5. The multilayer ceramic capacitor according to claim 4 , wherein the co-material contains at least some constituent elements of a ceramic material of the ceramic dielectric layers.

Assignees

• Murata Manufacturing Co

Inventors

• Doi Akitaka
• Yamaguchi Shinichi
• Suzuki Shoichiro

Classifications

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/0085

  Fried electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/306 Primary

  made by thin film techniques · CPC title