Apparatus having direct memory access controller and method for accessing data in memory

Patent metadata

Field	Value
Publication number	US-10282328-B2
Application number	US-201715641946-A
Country	US
Kind code	B2
Filing date	Jul 5, 2017
Priority date	Nov 7, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Disclosed are a direct memory access (DMA) apparatus and method. The DMA apparatus may include memory, a buffer, a DMA controller suitable for setting group regions from which data of the memory is to be read, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction, and a read module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction and reading the data of each even-numbered group region in the first direction.

First claim

What is claimed is:

1. A memory control apparatus for controlling a first memory under a control of a host, comprising:
a second memory;
a processor suitable for providing a search request for data stored in second memory; and
a search engine suitable for backward searching for the data stored in the second memory based on the data for the search request,
wherein the search engine comprises:
a buffer;
a direct memory access (DMA) controller suitable for setting group regions from which the data of the second memory is to be read in response to the search request, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction; and
a linear search hardware module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction, reading the data of each even-numbered group region written in the buffer in the first direction, analyzing the read data, and transmitting a result of the search to the processor,
wherein the first direction is one direction among addresses increasing direction and addresses decreasing direction, and the second direction is an opposite direction to the first direction.

2. The memory control apparatus of claim 1 , wherein the first direction is a forward direction in which a pointer for the buffer increases and the second direction is a backward direction in which the pointer for the buffer decreases.

3. The memory control apparatus of claim 2 , wherein:
the second memory includes a map table in which a logical block address of the host and a physical block address of the first memory are mapped, and
the data for the search request comprises data of the map table.

4. The memory control apparatus of claim 3 , wherein the data for the search request comprises information regarding reverse linear search, information about a search location of the map table and a search pattern.

5. The memory control apparatus of claim 4 , wherein:
the search pattern comprises logical block address data or physical block address data, and
the linear search hardware module is suitable for analyzing data accessed from the buffer and transmitting data identical with the search pattern to the processor.

6. The memory control apparatus of claim 3 , wherein:
the DMA controller is suitable for writing data in the buffer while changing a write pointer for the buffer in a predetermined direction, generating a buffer full signal when the writing of the data in the buffer is completed, and setting the set direction as a reverse direction, and
the linear search hardware module is suitable for reading the data of the buffer in a direction opposite the write direction of the DMA controller in response to the buffer full signal.

7. The memory control apparatus of claim 6 , wherein the buffer has a size identical with a data size of the group region.

8. A direct memory access (DMA) apparatus, comprising:
a memory;
a buffer;
a DMA controller suitable for setting group regions from which data of the memory is to be read, reading data of each odd-numbered group region in a first direction and writing the read data of each odd-numbered group region in the buffer in the first direction, and reading data of each even-numbered group region in the first direction and writing the read data of each even-numbered group region in the buffer in a second direction; and
a read module suitable for reading the data of each odd-numbered group region written in the buffer in the second direction and reading the data of each even-numbered group region in the first direction,
wherein the first direction is one direction among addresses increasing direction and addresses decreasing direction, and the second direction is an opposite direction to the first direction.

9. The DMA apparatus of claim 8 , wherein the first direction is a forward direction in which a pointer for the buffer increases and the second direction is a backward direction in which the pointer for the buffer decreases.

10. The DMA apparatus of claim 9 , wherein the buffer has a size identical with a group region size of the memory.

11. The DMA apparatus of claim 10 , wherein:
the DMA controller is suitable for writing data in the buffer while changing a write pointer for the buffer in a predetermined direction, generating a buffer full signal when the writing of the data in the buffer is completed, and setting the predetermined direction as a reverse direction, and
the read module is suitable for reading the data of the buffer in a direction opposite the write direction of the DMA controller in response to the buffer full signal.

12. The DMA apparatus of claim 11 , wherein the DMA controller is suitable for:
reversing a direction in which the write pointer for the buffer proceeds when the data of the buffer is read by the read module after generating the buffer full signal, and
resuming a write of data in the buffer in the set direction.

13. An operating method of a memory control apparatus comprising a second memory and controlling an operation of a first memory in response to a request from a host, the operating method comprising:
a step of setting group regions from which data of the second memory is to be read based on search request data of the second memory;
a first access step of reading data of a corresponding group region from the second memory in a first direction, writing the read data in the buffer in the first direction, and reading data of an odd-numbered group region written in the buffer in a second direction if the corresponding group region is an odd-numbered group region;
a second access step of reading data of a corresponding group region from the second memory in the first direction, writing the read data in the buffer in the second direction, and reading data of an even-numbered group written in the buffer in the first direction if the corresponding group region is an even-numbered group region; and
a search step of analyzing the read data and transmitting a result of the search,
wherein the first direction is one direction among addresses increasing direction and addresses decreasing direction, and the second direction is an opposite direction to the first direction.

14. The operating method of claim 13 , wherein the first direction is a forward direction in which a pointer for the buffer increases and the second direction is a backward direction in which the pointer for the buffer decreases.

15. The operating method of claim 14 , wherein:
the second memory comprises a map table in which a logical block address of the host and a physical block address of the first memory are mapped, and
the search request data comprises data of the map table.

16. The operating method of claim 15 , wherein the search request data comprises information regarding reverse linear search, information about a search location of the map table and a search pattern.

17. The operating method of claim 16 , wherein:
the search pattern comprises logical block address data or physical block address data, and
the search step comprises analyzing data accessed from the buffer and transmitting data identical with the search pattern.

18. The operating method of claim 15 , wherein the first access step or the second access step comprises:
writing data in the buffer while changing a w

Assignees

• Sk Hynix Inc

Inventors

• Lee Joung-Young

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/28

  DMA · CPC title