Method and system for hardware accelerated read-ahead caching

US10282301B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10282301-B2
Application numberUS-201715599201-A
CountryUS
Kind codeB2
Filing dateMay 18, 2017
Priority dateMay 18, 2017
Publication dateMay 7, 2019
Grant dateMay 7, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command. In response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation. The method further includes sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation and then causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request. The method further includes enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for read-ahead caching, the method comprising: determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command; in response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation; sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation; causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request; enabling the allocated ISGL and BSID to be used in connection with the read-ahead operation; transferring information describing the new LMID to a cache manager module; and enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID. 2. The method of claim 1 , further comprising: performing, by the cache manager module, a hash search using the row or strip number and identification information available in the new LMID; determining, during the hash search, that a hash hit has occurred for an identified row or strip; in response to determining that the hash hit has occurred, enabling the cache manager module to check if a flush is active on the identified row or strip; and in response to determining that the flush is not active, removing a corresponding cache segment from a dirty list. 3. The method of claim 1 , further comprising: performing, by the cache manager module, a hash search using the row or strip number and identification information available in the new LMID; determining, during the hash search, that a hash miss has occurred; in response to determining that a hash miss has occurred, enabling the cache manager module to allocate a new cache segment and add the cache segment to a hash. 4. The method of claim 3 , further comprising: sending the new LMID to a RAID manager module; and enabling the RAID manager module to execute the host I/O command by performing the read-ahead operation in which the RAID manager module performs a Direct Memory Access on data and provides the data to one or more buffers associated with the allocated ISGL and BSID. 5. The method of claim 4 , further comprising: obtaining the data from the RAID manager module, wherein the buffer manager updates the new cache segment with the data obtained from the RAID manager module. 6. The method of claim 1 , further comprising: determining whether a Cache Segment Identifier (CSID) corresponding to a row or strip is already stored in the new LMID or the ISGL; and in the event that the CSID corresponding to the row or strip is already stored in the new LMID or the ISGL, enabling the cache manager module to skip a hash search process. 7. The method of claim 1 , wherein the parameters contained in the buffer allocation request comprise one or more of an operation code, an ID number, a number of blocks required for the new LMID, and a starting arm. 8. The method of claim 7 , wherein the new LMID represents all information received from the host I/O command, but in a different format that is understandable by the buffer manager module and the cache manager module. 9. The method of claim 1 , further comprising: maintaining an LMID log that includes an LMID log head register and an LMID log tail register; and clearing the LMID log head register when the next LMID is read from the LMID log. 10. A memory control system, comprising: a host interface that receives one or more host Input/Output (I/O) commands; a storage interface that enables communication with a plurality of storage devices configured in a storage array; a microprocessor; and memory that includes computer-readable instructions that are executable by the microprocessor, the instructions including: instructions that determine that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command; instructions that, in response to determining that the read-ahead operation is to be performed, allocate a new Local Message Identifier (LMID) for the read-ahead operation; instructions that send a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation; instructions that cause the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request; instructions that enable the allocated ISGL and BSID to be used in connection with the read-ahead operation; instructions that transfer information describing the new LMID to a cache manager module; and instructions that enable the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID. 11. The memory control system of claim 10 , wherein the instructions further include: instructions that perform, with the cache manager module, a hash search using the row or strip number and identification information available in the new LMID; instructions that determine, during the hash search, that a hash hit has occurred for an identified row or strip; instructions that, in response to determining that the hash hit has occurred, enable the cache manager module to check if a flush is active on the identified row or strip; and instructions that, in response to determining that the flush is not active, remove a corresponding cache segment from a dirty list. 12. The memory control system of claim 10 , wherein the instructions further include: instructions that perform, with the cache manager module, a hash search using the row or strip number and identification information available in the new LMID; instructions that determine, during the hash search, that a hash miss has occurred; instructions that, in response to determining that a hash miss has occurred, enable the cache manager module to allocate a new cache segment and add the cache segment to a hash. 13. The memory control system of claim 12 , wherein the instructions further include: instructions that send the new LMID to a RAID manager module; and instructions that enable the RAID manager module to execute the host I/O command by performing the read-ahead operation in which the RAID manager module performs a Direct Memory Access on data and provides the data to one or more buffers associated with the allocated ISGL and BSID. 14. The memory control system of claim 13 , wherein the instructions further include: instructions that obtain the data from the RAID manager module, wherein the buffer manager updates the new cache segment with the data obtained from the RAID manager module. 15. The memory control system of claim 10 , wherein the instructions further include: instructions that determine whether a Cache Segment Identifier (CSID) corresponding to a row or strip is already stored in the new LMID or the ISGL; and instructions that, in the event that the CSID corresponding to the row or strip is already stored in the new LMID or the ISGL, enable the cache manager module to skip a hash search process. 16. The memory control system of claim 10 , wherein the parameters contained in the buffer allocation request comprise one or more of an operation code, an ID number, a number of blocks required for the new LMI

Assignees

Inventors

Classifications

  • Disk arrays, e.g. RAID, JBOD · CPC title

  • in relation to availability · CPC title

  • Employing a record carrier using a specific recording technology · CPC title

  • Plural cache memories · CPC title

  • Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

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What does patent US10282301B2 cover?
A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command. In response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation. The method further includes sending a…
Who is the assignee on this patent?
Avago Tech Int Sales Pte Lid
What technology area does this patent fall under?
Primary CPC classification G06F12/0868. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).