System and method for protecting firmware integrity in a multi-processor non-volatile memory system

Patent metadata

Field	Value
Publication number	US-10282251-B2
Application number	US-201615258688-A
Country	US
Kind code	B2
Filing date	Sep 7, 2016
Priority date	Sep 7, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A system and method is disclosed for managing firmware in a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors. Each of the plurality of processors may retrieve and check the integrity of firmware for a respective one of the other processors while the processor engaged in checking the respective one of the other processors is in an idle state.

First claim

We claim:

1. A method of managing transient errors in firmware in a multi-processor non-volatile memory (NVM) system, the NVM system having a first processor configured to execute a first portion of NVM system operations and a second processor configured to execute a second portion of NVM system operations different than the first portion of NVM system operations, the method comprising:
in response to a first processor in the NVM system entering a first state corresponding to a time period where no host command is pending for the first processor:
in the first state, the first processor retrieving executable instructions of the second processor stored in a volatile memory;
in the first state, the first processor verifying integrity of the retrieved executable instructions of the second processor; and
the first processor, in response to detecting an error in the retrieved executable instructions of the second processor, retrieving original executable instructions of the second processor from a non-volatile memory in the NVM system and replacing the executable instructions of the second processor in the volatile memory with the original executable instructions of the second processor.

2. The method of claim 1 , wherein the executable instructions of the second processor comprise a plurality of predetermined portions and wherein the first processor retrieving and verifying the integrity of the retrieved executable instructions of the second processor comprises the first processor:
sequentially, for each of the plurality of predetermined portions, retrieving a respective one of the plurality of portions and verifying the integrity of the respective one of the plurality of portions before retrieving and verifying a next respective one of the plurality of portions.

3. The method of claim 1 , wherein the first processor verifying integrity of the retrieved executable instructions of the second processor comprises the first processor generating parity information for the retrieved executable instructions of the second processor and determining whether the generated parity information matches previously stored parity information associated with the retrieved executable instructions.

4. The method of claim 1 , wherein the first processor verifying integrity of the retrieved executable instructions of the second processor comprises the first processor generating checksum information for the retrieved executable instructions of the second processor and determining whether the generated checksum information matches previously stored checksum information associated with the retrieved executable instructions.

5. The method of claim 4 , further comprising retrieving the previously stored checksum information from a volatile memory separate from the volatile memory containing the retrieved executable instructions.

6. A multi-processor non-volatile memory (NVM) system comprising:
a non-volatile memory having a plurality of non-volatile memory cells;
a first processor in communication with the non-volatile memory;
a second processor in communication with the non-volatile memory;
a volatile memory configured to hold executable instructions of the first processor in the volatile memory, and configured to hold executable instructions of the second processor in the volatile memory; and
wherein the first processor, during a first state of the first processor, is configured to check for errors in the executable instructions of the second processor in the volatile memory, wherein the first state of the first processor comprises a time period where no host command is pending for the first processor;
wherein the second processor, during a second state of the second processor, is configured to check for errors in the executable instructions of the first processor in the volatile memory, wherein the second state of the second processor comprises a time period where no host command is pending for the second processor; and
wherein the first processor is further configured to, in response to identifying an error in the executable instructions of the second processor held in the volatile memory, replace the executable instructions of the second processor held in the volatile memory with a copy of the executable instructions of the second processor retrieved from the non-volatile memory.

7. The multi-processor NVM system of claim 6 , wherein when the first processor and the second processor are in the first state and the second state, respectively, the first processor is configured to check for errors in the executable instructions of the second processor in the volatile memory concurrently with the second processor checking for errors in the executable instructions of the first processor in the volatile memory.

8. The multi-processor NVM system of claim 7 , further comprising:
the second processor further configured to, in response to identifying an error in the executable instructions of the first processor held in the volatile memory, apply an error correction algorithm to the executable instructions of the first processor, correct the identified error in the executable instructions of the first processor to generate corrected executable instructions and replace the executable instructions of the first processor in the volatile memory with the corrected executable instructions.

9. The multi-processor NVM system of claim 7 , wherein:
to check for errors in the executable instructions of the second processor, the first processor is configured to retrieve one portion of a plurality of portions of the executable instructions of the second processor from the volatile memory and check for any errors in the one portion before retrieving a next portion of the plurality of portions from the volatile memory and checking the next portion for any errors.

10. The multi-processor NVM system of claim 9 , wherein to check for any errors in a respective portion of the plurality of portions, the first processor is configured to generate checksum data for the respective portion and compare the generated checksum data with previously stored checksum data for the respective portion.

11. The multi-processor NVM system of claim 10 , wherein the non-volatile memory comprises a substrate formed with a three-dimensional memory structure.

12. The multi-processor NVM system of claim 9 , wherein the first processor further comprises a first cycle counter and a first portion pointer and wherein the first processor is configured to:
after checking for errors in a respective portion of the plurality of portions, update the first portion pointer to point to the respective portion, wherein the first portion pointer only points to a portion most recently checked for errors by the first processor; and
increment the first cycle counter each time all the plurality of portions of the executable instructions of the second processor has been checked by the first processor.

13. The multi-processor NVM system of claim 9 , wherein each of the plurality of portions comprises a physical page of memory.

14. The multi-processor NVM system of claim 6 , wherein the volatile memory comprises random access memory (RAM).

15. The multi-processor NVM system of claim 6 , wherein the volatile memory is located within the NVM system.

16. The multi-processor NVM system of claim 6 , wherein the volatile memory is a host memory buffer located in a host outside of the multi-processor NVM system.

17. The multi-processor NVM system of claim 16 , wherein when the first processor detects an error in the executable instructions of the second processor stored in the h

Assignees

• Sandisk Technologies Llc

Inventors

• Gusev Ilya
• Zagalsky Yevgeny
• Kantor Beniamin
• Benisty Shay
• Hahn Judah Gamliel

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title