Method for a stage optimized high speed adder

Patent metadata

Field	Value
Publication number	US-10282170-B2
Application number	US-201715659393-A
Country	US
Kind code	B2
Filing date	Jul 25, 2017
Priority date	Mar 15, 2013
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.

First claim

What is claimed is:

1. A method implemented by a parallel adder, the method comprising:
receiving a set of one bit inputs in parallel; and
adding the set of one bit inputs in parallel in a first stage and second stage of the parallel adder to generate an output that is a sum of the set of one bit inputs, the first stage including at least one four to one adder and the second stage including at least one three to two carry save adder.

2. The method of claim 1 , wherein the output is a non-redundant value.

3. The method of claim 1 , wherein the first stage includes at least one two to one adder.

4. The method of claim 1 , wherein the second stage includes at least two fewer adders than the first stage.

5. The method of claim 1 , wherein the second stage includes multiple levels that are configured to utilize propagation delay differences between outputs of the first stage into multiple levels of the second stage.

6. The method of claim 1 , wherein at least one four to one adder in the first stage includes at least one four to one multiplexor.

7. A parallel adder circuit, the parallel adder circuit comprising:
a first stage to receive a set of one bit inputs in parallel, first stage to add the set of one bit inputs in parallel and output a set of sums to a second stage, the first stage including at least one four to one adder; and
the second stage to generate an output that is a sum of the set of one bit inputs, the second stage including at least one three to two carry save adder.

8. The parallel adder circuit of claim 7 , wherein the output is a non-redundant value.

9. The parallel adder circuit of claim 7 , wherein the first stage includes at least one two to one adder.

10. The parallel adder circuit of claim 7 , wherein the second stage includes at least two fewer adders than the first stage.

11. The parallel adder circuit of claim 7 , wherein the second stage includes multiple levels that are configured to utilize propagation delay differences between outputs of the first stage into multiple levels of the second stage.

12. The parallel adder circuit of claim 7 , wherein at least one four to one adder in the first stage includes at least one four to one multiplexor.

13. A processor to perform parallel adding, the processor comprising:
an interconnect to enable communication within the processor;
a set of execution units coupled to the interconnect to execute instructions; and
at least one arithmetic unit including a first stage to receive a set of one bit inputs in parallel, first stage to add the set of one bit inputs in parallel and output a set of sums to a second stage, the first stage including at least one four to one adder, and the second stage to generate an output that is a sum of the set of one bit inputs, the output being a non-redundant value, the second stage including at least one three to two carry save adder.

14. The processor of claim 13 , wherein the output is a non-redundant value.

15. The processor of claim 13 , wherein the first stage includes at least one two to one adder.

16. The processor of claim 13 , wherein the second stage includes at least two fewer adders than the first stage.

17. The processor of claim 13 , wherein the second stage includes multiple levels that are configured to utilize propagation delay differences between outputs of the first stage into multiple levels of the second stage.

18. The processor of claim 13 , wherein at least one four to one adder in the first stage includes at least one four to one multiplexor.

19. A non-transitory machine-readable medium having instructions stored therein, which when executed by a processor, cause the processor to perform a set of operations comprising:
receiving a set of one bit inputs in parallel; and
adding the set of one bit inputs in parallel in a first stage and second stage to generate an output that is a sum of the set of one bit inputs, the output being a non-redundant value, the adding utilizing propagation delay differences between outputs of the first stage into multiple levels of the second stage.

20. The non-transitory machine-readable medium of claim 19 , wherein the output is a non-redundant value.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F7/5045 Primary

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