Control device, system, and computer program product

Patent metadata

Field	Value
Publication number	US-10281970-B2
Application number	US-201514929732-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Jan 20, 2012
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.

First claim

What is claimed is:

1. A control device comprising:
a setting circuit configured to, when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming a system, the system including a plurality of elements, power to each element being individually controlled, from the sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped, set, a mode indicating an operation state of the system during a time of resuming from the sleep state according to a system processing time indicating a time required for the plurality of interrupt processes that is executed so as to at least partially overlap each other, the overlapping interrupt processes being executed after the system resumes from the sleep state, the system processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process starts, the interrupt processing time indicating a time required for the interrupt process.

2. A control device comprising:
a setting circuit configured to, when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming a system, the system operating in any of a plurality of modes with different amounts of power consumption, from the sleep state, select and set from the plurality of modes a mode indicating an operation state of the system during a time of resuming from the sleep state on the basis of a system processing time indicating a time required for the plurality of interrupt processes that is executed so as to at least partially overlap each other, the overlapping interrupt processes being executed after the system resumes from the sleep state, the system processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process starts, the interrupt processing time indicating a time required for the interrupt process.

3. A control device comprising:
a setting circuit configured to, when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming a system, the system operating in any of a plurality of modes with different amounts of power consumption, from the sleep state,
set a mode indicating an operation state of the system during a time of resuming from the sleep state to a low mode of the plurality of modes when a system processing time, which indicates a time required for the plurality of interrupt processes that is executed so as to at least partially overlap each other, is lower than a predetermined value, the overlapping interrupt processes being executed after the system resumes from the sleep state, the system processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process starts, the interrupt processing time indicating a time required for the interrupt process, and
set the mode indicating the operation state of the system during the time of resuming from the sleep state to a high mode of the plurality of modes when the system processing time is equal to or higher than the predetermined value, and
the high mode is a mode with a higher amount of power consumption than that of the low mode.

4. An information processing system operating in any of a plurality of modes with different amounts of power consumption, the system being configured to perform functions, the functions comprising:
when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming the system from the sleep state,
causing the system during a time of resuming from the sleep state to operate in a low mode of the plurality of modes when a system processing time, which indicates a time required for the plurality of interrupt processes that is executed so as to at least partially overlap each other, is lower than a predetermined value, the overlapping interrupt processes being executed after the system resumes from the sleep state, the system processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process starts, the interrupt processing time indicating a time required for the interrupt process, and
causing the system during the time of resuming from the sleep state to operate in a high mode of the plurality of modes when the system processing time is equal to or higher than the predetermined value, wherein
the high mode is a mode with a higher amount of power consumption than that of the low mode.

5. An information processing system operating in any of a plurality of modes with different amounts of power consumption, the system being configured to perform functions, the functions comprising:
when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming the system from the sleep state, causing the system during a time of resuming from the sleep state to operate in a mode, of the plurality of modes, that is based on a processing time of the plurality of interrupt processes that is executed so as to at least partially overlap each other, the overlapping interrupt processes being executed after the system resumes from the sleep state, the processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process starts, the interrupt processing time indicating a time required for the interrupt process.

6. A control device comprising:
a setting circuit configured to, when there occurs in a sleep state a plurality of interrupt waits for waiting for starts of a plurality of interrupt processes each of which is a factor for resuming a system, the system including a plurality of elements, power to each element being individually controlled, from the sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped, set a mode indicating an operation state of the system during a time of resuming from the sleep state such that, as a system processing time, which indicates a time required for the plurality of interrupt processes that is executed so as to at least partially overlap each other, increases, the number of elements which are operated increases, the overlapping interrupt processes being executed after the system resumes from the sleep state, the system processing time being determined based on information in which an interrupt type, an interrupt latency, and an interrupt processing time are associated with each other, the interrupt latency indicating a time that elapses from when the interrupt wait occurs to when the interrupt process st

Assignees

• Toshiba Memory Corp

Inventors

• Haruki Hiroyoshi
• Fujisaki Koichi
• Segawa Junichi
• Shirai Satoshi
• Shirota Yusuke
• Shibata Akihiro
• Tarui Masaya
• Kimura Tetsuro
• Kanai Tatsunori
• Toyama Haruhiko

Classifications

• Y02D10/171

  Cross-Sectional Technologies · mapped topic

• Y02D10/174

  Cross-Sectional Technologies · mapped topic

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• Y02D10/128

  Cross-Sectional Technologies · mapped topic

• G06F1/3237

  by disabling clock generation or distribution · CPC title