Method for encoding real number M-ary signal and encoding apparatus using same

Patent metadata

Field	Value
Publication number	US-10277434-B2
Application number	US-201515561904-A
Country	US
Kind code	B2
Filing date	Apr 21, 2015
Priority date	Mar 27, 2015
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N 1 number of M 1 -ary signals, a second signal generator which receives the second input code and generates N 2 number of M 2 -ary signals, and a first time division multiplexing module which temporally multiplexes the N 1 number of M 1 -ary signals and the N 2 number of M 2 -ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A 2 /A 1 ) used for M 1 -ary and M 2 -ary signals to minimize a transmission error rate.

First claim

The invention claimed is:

1. An M-ary encoding apparatus, comprising:
a coding unit configured to code, from binary data, to generate a first coded sequence and a second coded sequence, the coding unit including a serial-parallel converter configured to convert serial binary data to K-bit parallel data and a symbol mapper configured to map the K-bit parallel data to the first coded sequence and the second coded sequence;
a signal generator configured to generate: (1) from the first coded sequence, a first number of M 1 -ary signals; and (2) from the second coded sequence, a second number of M 2 -ary signals; and
a multiplexer configured to multiplex the first number of M 1 -ary signals and the second number of M 2 -ary signals to generate a multiplexed M-ary signal, where M 1 and M 2 are integers.

2. The M-ary encoding apparatus of claim 1 , wherein the coding unit is configured to code: (1) a first set of K binary data bits to generate a first portion of the first coded sequence and the second coded sequence; and (2) one or more further sets of K binary data bits to generate one or more further portions of the first coded sequence and the second coded sequence.

3. The M-ary encoding apparatus of claim 1 , wherein the multiplexer is configured to time and/or frequency multiplex the first number of M 1 -ary signals and the second number of M 2 -ary signals.

4. The M-ary encoding apparatus of claim 1 , wherein the first number of M 1 -ary signals are N 1 number of M 1 -ary signals and the second number of M 2 -ary signals are N 2 number of M 2 -ary signals, where N 1 and N 2 are integers.

5. The M-ary encoding apparatus of claim 1 , further comprising:
a processor configured to:
determine, as a determined result, any of: (1) an error rate of a channel; (2) a noise level associated with the channel; or (3) a signal to noise ratio (SNR) per bit;
establish a real number M based on the determined result; and
determine M 1 , as M 1 =[M], and M 2 , as M 2 =[M]+1, where [M] is a greatest integer which is not greater than the real number M.

6. The M-ary encoding apparatus of claim 2 , wherein:
the first number of M 1 -ary signals are N 1 number of M 1 -ary signals and the second number of M 2 -ary signals are N 2 number of M 2 -ary signals, where N 1 and N 2 are integers; and
K is determined using an equation K=[N 1 log 2 M 1 +N 2 log 2 M 2 ].

7. The M-ary encoding apparatus of claim 4 , wherein:
N=N 1 +N 2 ;
N j (j=1 or 2) is determined based on a transmission efficiency level and a calculation complexity level;
the transmission efficiency level includes a mean transmission bit number per signal component of the multiplexed M-ary signal; and
the mean transmission bit number per signal component is calculated as [N 1 log 2 M 1 +N 2 log 2 M 2 ]/N.

8. The M-ary encoding apparatus of claim 7 , wherein
N j (j=1 or 2) is 1 on a condition that M j (j=1 or 2) is 2, 4, 8, 16, or 32,
N j (j=1 or 2) is 2 on a condition that M j (j=1 or 2) is 3, 6, 12, or 23,
N j (j=1 or 2) is 3 on a condition that M j (j=1 or 2) is 21 or 26,
N j (j=1 or 2) is 4 on a condition that M j (j=1 or 2) is 5, 10, 20, or 27,
N j (j=1 or 2) is 5 on a condition that M j (j=1 or 2) is 7, 11, 13, 14, 19, 22, 25, or 28,
N j (j=1 or 2) is 6 on a condition that M j (j=1 or 2) is 9, 15, 18, or 29,
N j (j=1 or 2) is 7 on a condition that M j (j=1 or 2) is 24,
N j (j=1 or 2) is 8 on a condition that M j (j=1 or 2) is 30,
N j (j=1 or 2) is 10 on a condition that M j (j=1 or 2) is 31, and
N j (j=1 or 2) is 12 on a condition that M j (j=1 or 2) is 17.

9. The M-ary encoding apparatus of claim 1 , wherein:
the signal generator includes:
a first pulse amplitude modulation (PAM) generator configured to generate the first number of first PAM signals, the first PAM signals having M 1 number of voltage levels, and
a second PAM generator configured to generate the second number of second PAM signals, the second PAM signals having M 2 number of voltage levels; and

the multiplexer includes a first multiplexing device configured to temporally multiplex the first PAM signals and the second PAM signals.

10. The M-ary encoding apparatus of claim 9 , wherein:
the signal generator further includes:
a third PAM generator configured to generate the first number of third PAM signals, the third PAM signals having M 1 number of voltage levels, and
a fourth PAM generator configured to generate the second number of fourth PAM signals, the fourth PAM signals having M 2 number of voltage levels; and

the multiplexer further includes a second multiplexing device configured to temporally multiplex the third PAM signals and the fourth PAM signals.

11. The M-ary encoding apparatus of claim 10 , wherein:
the first multiplexing device is configured to temporally multiplex the first PAM signals and the second PAM signals such that the first PAM signals are first in time and the second PAM signals are second in time, as a first PAM multiplexed signal; and
the second multiplexing device is configured to multiplex the third PAM signals and the fourth PAM signals such that the third PAM signals are first in time and the fourth PAM signals are second in time, as a second PAM multiplexed signal.

12. The M-ary encoding apparatus of claim 11 , further comprising:
a first multiplier configured to multiply the first PAM multiplexed signal by a cosine signal to generate an I channel modulation signal;
a second multiplier configured to multiply the second PAM multiplexed signal by a sine signal, which is orthogonal to the cosine signal, to generate a Q channel modulation signal; and
an adder configured to sum the I channel modulation signal and the Q channel modulation signal.

13. The M-ary encoding apparatus of claim 1 , further comprising:
a K-frequency divider configured to divide an input clock signal by K to generate a divided clock signal; and
an N-frequency multiplier configured to multiply a frequency of the divided clock signal by N to generate a multiplied clock signal, wherein:
the symbol mapper is configured to operate in response to the divided clock signal, and
the signal generator is configured to operate in response to the multiplied clock signal.

14. The M-ary encoding apparatus of claim 1 , wherein the multiplexed M-ary signal is one of: (1) a N time-dimensional M-ary PAM signal; (2) a N time-dimensional M-ary amplitude shift keying (ASK) signal; (3) a N time-dimensional M-ary frequency shift keying (FSK) signal; (4) a N time-dimensional Mary phase shift keying (PSK) signal; (5) a N time-dimensional M-ary quadrature amplitude modulation (QAM) signal; or (6) a N time-dimensional and L frequency dimensional M-ary amplitude, phase, and frequency modulation (APFSK) signal.

15. The M-ary encoding apparatus of claim 14 , further comprising a processor configured to allocate one or more codes for a channel environment having inter-channel interference (ICI) above a threshold such that frequencies are skipped when generating the N time-dimensional and L frequency-dimensional M-ary APFSK signal.

16. An M-ary encoding method, the method comprising:
coding, from binary data, to generate a first coded sequence and a second coded sequence by converting serial binary data to K-bit parallel data and mapping, by a symbol mapper, the K-bit parallel data to the first coded sequence and the second coded sequence;
generating: (1) from the first coded sequence, a first number of M 1 -ary signals; and (2) from the second coded sequence, a second number of M 2 -ary signals; and
multiplexing the firs

Assignees

• Idac Holdings Inc

Inventors

• Chung Hae
• Chung Han

Classifications

• H04L27/366

  Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator · CPC title

• H03M5/20 Primary

  the pulses having more than three levels · CPC title

• H03M7/30

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• H04L25/4917 Primary

  using multilevel codes · CPC title

• H04L27/04

  Modulator circuits; Transmitter circuits · CPC title