Low power barrier modulated cell for storage class memory

Patent metadata

Field	Value
Publication number	US-10276792-B2
Application number	US-201815890296-A
Country	US
Kind code	B2
Filing date	Feb 6, 2018
Priority date	Apr 20, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.

First claim

What is claimed is:

1. A method for fabricating a portion of a memory array, comprising:
forming an alternating stack of word line layers and dielectric layers;
etching a memory hole extending through the alternating stack of word line layers and dielectric layers;
recessing a portion of a first word line layer of the word line layers subsequent to etching the memory hole;
depositing one of a layer of amorphous germanium or a layer of amorphous silicon germanium within a first region of the recessed portion of the first word line layer;
depositing a layer of metal oxide adjacent to the one of the layer of amorphous germanium or the layer of amorphous silicon germanium; and
depositing a conducting material within the memory hole subsequent to depositing the layer of metal oxide.

2. The method of claim 1 , wherein:
the depositing the layer of metal oxide includes depositing the layer of metal oxide within a second region of the recessed portion of the first word line layer.

3. The method of claim 1 , wherein:
the layer of metal oxide comprises a layer of titanium oxide.

4. The method of claim 1 , wherein:
the word line layers comprise a word line material;
the dielectric layers comprise a dielectric material; and
the recessing the portion of the first word line layer includes performing an etching process that removes the word line material while being highly selective to the dielectric material.

5. The method of claim 1 , wherein:
the word line layers comprise titanium nitride; and
the dielectric layers comprise silicon dioxide.

6. The method of claim 1 , further comprising:
depositing both the layer of amorphous germanium and the layer of amorphous silicon germanium within the first region of the recessed portion of the first word line layer.

7. The method of claim 1 , wherein:
the conducting material comprises tungsten.

8. A method for fabricating a portion of a memory array, comprising:
etching a memory hole extending through an alternating stack of word line layers and dielectric layers;
recessing a portion of a first word line layer of the word line layers subsequent to etching the memory hole;
filling a first region of the recessed portion of the first word line layer with one of a layer of amorphous germanium or a layer of amorphous silicon germanium;
depositing a layer of metal oxide adjacent to the one of the layer of amorphous germanium or the layer of amorphous silicon germanium; and
depositing a conducting material within the memory hole subsequent to depositing the layer of metal oxide.

9. The method of claim 8 , wherein:
the depositing the layer of metal oxide includes depositing the layer of metal oxide within a second region of the recessed portion of the first word line layer.

10. The method of claim 8 , wherein:
the layer of metal oxide comprises a layer of titanium oxide.

11. The method of claim 8 , wherein:
the recessing the portion of the first word line layer includes performing an etching process that removes the word line material while being highly selective to the dielectric material.

12. The method of claim 8 , wherein:
the word line layers comprise titanium nitride; and
the dielectric layers comprise silicon dioxide.

13. The method of claim 8 , further comprising:
depositing both the layer of amorphous germanium and the layer of amorphous silicon germanium within the first region of the recessed portion of the first word line layer.

14. A method for fabricating a portion of a memory array, comprising:
forming an alternating stack of word line layers and dielectric layers above a substrate;
etching a memory hole extending through the alternating stack of word line layers and dielectric layers;
recessing a portion of a first word line layer of the word line layers subsequent to etching the memory hole;
depositing a layer of amorphous germanium and a layer of amorphous silicon germanium within a first region of the recessed portion of the first word line layer; and
depositing a layer of metal oxide adjacent to the layer of amorphous germanium or the layer of amorphous silicon germanium, the depositing the layer of metal oxide includes depositing the layer of metal oxide within a second region of the recessed portion of the first word line layer.

15. The method of claim 14 , further comprising:
depositing a conducting material within the memory hole subsequent to depositing the layer of metal oxide.

16. The method of claim 14 , wherein:
the layer of metal oxide comprises a layer of titanium oxide.

17. The method of claim 14 , wherein:
the recessing the portion of the first word line layer includes performing an etching process that removes the word line material while being highly selective to the dielectric material.

18. The method of claim 14 , wherein:
the word line layers comprise titanium nitride; and
the dielectric layers comprise silicon dioxide.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Ming-Che
• Kumar Tanmay

Classifications

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• H01L27/2454

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L45/146 Primary

  Electricity · mapped topic