Scalable process for the formation of self aligned, planar electrodes for devices employing one or two dimensional lattice structures

Patent metadata

Field	Value
Publication number	US-10276698-B2
Application number	US-201514919312-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 21, 2015
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A method of forming an electrical device that includes forming a gate dielectric layer over a gate electrode, forming source and drain electrodes on opposing sides of the gate electrode, wherein one end of the source and drain electrodes provides a coplanar surface with the gate dielectric, and positioning a 1D or 2D nanoscale material on the coplanar surface to provide the channel region of the electrical device.

First claim

What is claimed is:

1. A method of forming an electrical device comprising:
forming a gate dielectric layer on a single layer insulating substrate and an upper surface and sidewall surfaces of a gate electrode on the single layer insulating substrate;
forming source and drain electrodes on opposing sides of the gate electrode on the gate dielectric layer electrically isolating the source and drain electrodes from the single layer insulating substrate, wherein top surfaces of the source and drain electrodes provide a coplanar surface with a top surface of the gate dielectric layer; and
positioning a one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof on the coplanar surface to provide a channel region of the electrical device.

2. The method of claim 1 , wherein forming the gate electrode comprises;
forming a photoresist layer on the single layer insulating substrate;
patterning the photoresist layer to provide an opening;
depositing a first electrically conductive material in the opening; and
removing a remaining portion of the photoresist layer.

3. The method of claim 1 , wherein the dielectric material that provides the gate dielectric layer is conformally deposited.

4. The method of claim 1 , wherein said forming the source and drain electrodes on opposing sides of the gate electrode comprises depositing a second electrically conductive material on the gate dielectric layer that is present over the gate electrode; and planarizing the second electrically conductive material to provide the source and drain electrodes having said coplanar surface with the gate dielectric layer.

5. The method of claim 1 , wherein the one dimensional (1D) nanoscale material, the two dimensional (2D) nanoscale material, or the combination thereof comprises carbon nanotubes, graphene, transition metal dichalcogenides, black phosphorus or a combination thereof.

6. The method of claim 1 , wherein positioning the one dimensional (1D) nanoscale material, the two dimensional (2D) nanoscale material, or the combination thereof comprises in-situ material growth, chemical vapor deposition, electric field-assisted assembly from solution, or material exfoliation and transfer.

7. A method of forming an electrical device comprising:
forming a gate dielectric layer on a planarized single layer insulating substrate and an upper surface and sidewall surfaces of a gate electrode on the planarized single layer insulating substrate;
forming source and drain electrodes on opposing sides of the gate electrode on the gate dielectric layer electrically isolating the source and drain electrodes from the planarized single layer insulating substrate, wherein top surfaces of the source and drain electrodes provide a coplanar surface with a top surface of the gate dielectric layer; and
positioning a one dimensional (1D) nanoscale material, a two dimensional (2D) nanoscale material, or a combination thereof on the coplanar surface to provide a channel region of the electrical device, wherein the 1D or 2D nanoscale material comprises carbon nanotubes, graphene, black phosphorus or a combination thereof.

8. The method of claim 7 , wherein forming the gate electrode comprises;
forming a photoresist layer on the planarized single layer insulating substrate;
patterning the photoresist layer to provide an opening;
depositing a first electrically conductive material in the opening; and
removing a remaining portion of the photoresist layer.

9. The method of claim 7 , wherein said forming the source and drain electrodes on opposing sides of the gate electrode comprises depositing a second electrically conductive material on the gate dielectric layer that is present over the gate electrode.

10. The method of claim 9 further comprising planarizing the second electrically conductive material to provide the source and drain electrodes having said coplanar surface with the gate dielectric layer.

11. The method of claim 7 , wherein positioning the one dimensional (1D) nanoscale material, the two dimensional (2D) nanoscale material, or the combination thereof comprises in-situ material growth, chemical vapor deposition, electric field-assisted assembly from solution, or material exfoliation and transfer.

Assignees

• IBM

Inventors

• Engel Michael
• Steiner Mathias B

Classifications

• H01L29/778

  Electricity · mapped topic

• H01L29/66045

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/1606

  Electricity · mapped topic

• H01L29/66969 Primary

  Electricity · mapped topic