Time-of-fight pixel including in-pixel buried channel transistors

Patent metadata

Field	Value
Publication number	US-10276628-B2
Application number	US-201715596136-A
Country	US
Kind code	B2
Filing date	May 16, 2017
Priority date	May 17, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An imaging device, including a monolithic semiconductor integrated circuit substrate, comprises a focal plane array of pixel cells. Each one of the pixel cells includes a gate overlying a region of the substrate operable to convert incident radiation into charge carriers. The pixel also includes a CMOS readout circuit including at least one output transistor in the substrate. The pixel further includes a charge coupled device section on the substrate adjacent the gate, the charge coupled device section including a sense node to receive charge carriers transferred from the region of the substrate beneath the gate. The sense node is coupled to the output transistor. The pixel also includes a reset switch coupled to the sense node. The pixel's charge coupled device section has a buried channel region. The pixel also includes one or more bias enabling switches operable to enable a bias voltage to be applied to the gate. At least one of the reset switch or the one or more bias enabling switches is formed in the buried channel region.

First claim

What is claimed is:

1. An imaging device including a monolithic semiconductor integrated circuit substrate, the imaging device comprising a focal plane array of pixel cells, each one of the pixel cells comprising:
a gate overlying a region of the substrate operable to convert incident radiation into charge carriers;
a CMOS readout circuit including at least one output transistor in the substrate;
a charge coupled device section on the substrate adjacent the gate, the charge coupled device section including a sense node to receive charge carriers transferred from the region of the substrate beneath the gate, wherein the sense node is coupled to the output transistor, and wherein the charge coupled device section has a buried channel region;
a reset switch coupled to the sense node; and
one or more bias enabling switches operable to enable a bias voltage to be applied to the gate,
wherein at least one of the reset switch or the one or more bias enabling switches is formed in the buried channel region.

2. The imaging device of claim 1 wherein the reset switch is a buried channel transistor.

3. The imaging device of claim 2 wherein the reset switch is a NMOS FET.

4. The imaging device of claim 2 wherein the reset switch is a buried channel transistor having a threshold voltage no greater than zero volts.

5. The imaging device of claim 1 wherein each of the one or more bias enabling switches is a buried channel transistor.

6. The imaging device of claim 5 wherein each of the one or more bias enabling switches is a NMOS FET.

7. The imaging device of claim 5 wherein each of the one or more bias enabling switches is a buried channel transistor having a threshold voltage no greater than zero volts.

8. The imaging device of claim 1 wherein the reset switch and each of the one or more bias enabling switches is formed in the buried channel region.

9. The imaging device of claim 8 wherein each of the reset switch and the one or more bias enabling switches includes a buried channel transistor.

10. The imaging device of claim 8 wherein each of the reset switch and the one or more bias enabling switches is a NMOS FET having a threshold voltage no greater than zero volts.

11. The imaging device of claim 1 wherein the buried channel region is a buried channel implant region.

12. A time of flight camera system comprising:
a modulated light source;
an imaging sensor including a two-dimensional array of demodulation pixels, the imaging sensor operable to detect light generated by the modulated light source and reflected by an object, wherein each demodulation pixel comprises:
an integration gate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate;
a CMOS readout circuit including at least one output transistor in the substrate;
a charge coupled device section on the substrate adjacent the integration gate, the charge coupled device section including a sense node connected to the output transistor, and including at least one charge coupled device for transferring charge from the underlying portion of the substrate to the sensing node, wherein the charge coupled device section has a buried channel region;
a reset switch coupled to the sense node; and
one or more bias enabling switches operable to enable a bias voltage to be applied to the integration gate,
wherein the reset switch and the one or more bias enabling switches are formed in the buried channel region.

13. The time of flight camera system of claim 12 further including a processor operable to convert a two-dimensional gray scale image, based on output signals from the demodulation pixels, to a three-dimensional image.

14. The time of flight camera system of claim 12 wherein each of the reset switch and the one or more bias enabling switches is a buried channel transistor.

15. The time of flight camera system of claim 12 wherein each of the reset switch and the one or more bias enabling switches is a NMOS FET having a threshold voltage no greater than zero volts.

16. The time of flight camera system of claim 12 wherein the buried channel region is a buried channel implant region.

17. A method of operating a demodulation pixel that includes: an integration gate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate; a CMOS readout circuit including at least one output transistor in the substrate; a charge coupled device section on the substrate adjacent the integration gate, the charge coupled device section including a sense node connected to the output transistor, and including at least one charge coupled device for transferring charge from the underlying portion of the substrate to the sensing node, wherein the charge coupled device section has a buried channel region; a reset switch coupled to the sense node; and one or more bias enabling switches operable to enable a bias voltage to be applied to the integration gate, wherein at least one of the reset switch or the one or more bias enabling switches is a buried channel transistor in the buried channel region,
the method comprising:
applying a voltage to a respective gate of the one or more bias enabling switches so as to permit a bias voltage to be applied to the integration gate of the pixel;
accumulating photo-generated charge in the underlying portion of the substrate;
transferring the photo-generated charge from the underlying portion of the substrate to the sensing node;
using the readout circuit to read out a signal based on the charge in the sense node; and
applying a voltage to a gate of the reset switch so as to reset the sense node.

Assignees

• Ams Sensors Singapore Pte Ltd

Inventors

• Gancarz Radoslaw Marcin
• Furrer Daniel
• Vaello Paños Miguel Bruno
• Beer Stephan

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N5/378

  Electricity · mapped topic

• G01S7/4863

  Detector arrays, e.g. charge-transfer gates · CPC title

• H04N13/271

  wherein the generated image signals comprise depth maps or disparity maps · CPC title