Methods, structures and devices for intra-connection structures

Patent metadata

Field	Value
Publication number	US-10276580-B2
Application number	US-201715658660-A
Country	US
Kind code	B2
Filing date	Jul 25, 2017
Priority date	May 15, 2014
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.

First claim

What is claimed is:

1. A method comprising:
forming a first gate structure and a first source/drain region adjacent to the first gate structure on a substrate;
forming a first conductive material between the first gate structure and the first source/drain region, wherein the first conductive material is in contact with part of the first gate structure and in contact with part of the first source/drain region;
forming a dielectric material that covers at least a portion of a top horizontal surface of the first gate structure; and
forming a spacer material on a sidewall of the first gate structure, wherein the dielectric material, the first conductive material, and the spacer material are positioned at a substantially same height to form a substantially planar surface comprising uppermost surfaces of the respective dielectric material, first conductive material, and spacer material relative to the substrate, the substantially planar surface being higher than the top horizontal surface of the first gate structure relative to the substrate.

2. The method of claim 1 , wherein the first conductive material is configured to electrically connect the first gate structure and the first source/drain region.

3. The method of claim 1 , wherein:
the first gate structure is associated with a first transistor; and
the first source/drain region is associated with a second transistor.

4. The method of claim 3 , further comprising forming a second conductive material between a second source/drain region associated with the first transistor and a second gate structure associated with the second transistor to electrically connect the second source/drain region and the second gate structure.

5. The method of claim 1 , further comprising:
forming a first dielectric material on the first conductive material;
forming a second source/drain region adjacent to the first gate structure; and
forming a second conductive material on the second source/drain region, wherein the spacer material is formed between the second conductive material and the first gate structure.

6. The method of claim 5 , further comprising:
forming a conductive structure on the second conductive material for applying a voltage on the second source/drain region, the conductive structure including one or more third conductive materials.

7. The method of claim 1 , wherein a top surface of the first conductive material is higher than the top horizontal surface of the first gate structure relative to the substrate.

8. The method of claim 1 , wherein the first conductive material is in contact with a second sidewall of the first gate structure.

9. The method of claim 1 , wherein the first conductive material is in contact with a top surface of the first source/drain region.

10. A method comprising:
forming a gate structure associated with a first transistor;
forming a source/drain region associated with a second transistor, the source/drain region being adjacent to the gate structure, wherein a portion of the source/drain region is disposed in a same vertical level as the gate structure;
forming an intra-connection conductive material disposed in contact with a first sidewall of the gate structure and a top surface of the source/drain region, the intra-connection conductive material covering a first portion of a top surface of the gate structure;
forming a dielectric material that covers at least a portion of a top horizontal surface of the gate structure; and
forming a spacer material on a second sidewall of the gate structure, wherein the dielectric material, the intra-connection conductive material, and the spacer material are positioned at a substantially same height to form a substantially planar surface comprising uppermost surfaces of the respective dielectric material, intra-connection conductive material, and spacer material relative to a substrate on which the gate structure is formed, the substantially planar surface being higher than the top horizontal surface of the gate structure relative to the substrate.

11. The method of claim 10 , wherein the first transistor corresponds to a first pull-up transistor of a static random access memory (SRAM) cell, and the second transistor corresponds to a second pull-up transistor of the SRAM cell.

12. A method comprising:
forming a first gate structure and a first source/drain region adjacent to the first gate structure on a substrate;
forming a first dielectric material on at least a portion of a top horizontal surface of the first gate structure;
forming a spacer material on a sidewall of the first gate structure, wherein the first dielectric material, a first conductive material, and the spacer material are positioned at a substantially same height to form a substantially planar surface comprising uppermost surfaces of the first dielectric material, the first conductive material, and the spacer material relative to the substrate, the substantially planar surface being higher than the top horizontal surface of the first gate structure relative to the substrate;
removing the first dielectric material to expose at least part of the first source/drain region; and
forming the first conductive material between the first gate structure and the first source/drain region.

13. The method of claim 12 , wherein the first conductive material is configured to electrically connect the first gate structure and the first source/drain region.

14. The method of claim 12 , wherein:
the first gate structure is associated with a first transistor; and
the first source/drain region is associated with a second transistor.

15. The method of claim 14 , further comprising forming a second conductive material between a second source/drain region associated with the first transistor and a second gate structure associated with the second transistor to electrically connect the second source/drain region and the second gate structure.

16. The method of claim 12 , further comprising:
forming a second source/drain region adjacent to the first gate structure; and
forming a second conductive material on the second source/drain region, wherein the spacer material is formed between the second conductive material and the first gate structure.

17. The method of claim 16 , further comprising:
forming a conductive structure on the second conductive material for applying a voltage on the second source/drain region, the conductive structure including one or more third conductive materials.

18. The method of claim 12 , wherein a top surface of the first conductive material is higher than the top horizontal surface of the first gate structure relative to the substrate.

19. The method of claim 12 , wherein the first conductive material is in contact with a second sidewall of the first gate structure.

20. The method of claim 12 , wherein the first conductive material is in contact with a top surface of the first source/drain region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Feng-Ming
• Hsu Kuo-Hsiu

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic