Power module

US10276522B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10276522-B2
Application numberUS-201514819446-A
CountryUS
Kind codeB2
Filing dateAug 6, 2015
Priority dateOct 15, 2014
Publication dateApr 30, 2019
Grant dateApr 30, 2019

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance.

First claim

Opening claim text (preview).

What is claimed is: 1. A power module, comprising: a first substrate comprising a first circuit-patterned layer and a first insulating layer, the first insulating layer having a first surface on which the first circuit-patterned layer is located; a first power chip having a first bottom surface and a first top surface; a first bonding material bonding the first power chip to the first circuit-patterned layer connected to the first bottom surface; and at least one first spacer located and employed as supports between a surface of the first circuit-patterned layer facing toward the first power chip and the bottom surface, the first spacer having a first height; a second substrate comprising a second insulating layer and a second circuit-patterned layer, wherein the second insulating layer has a second surface, and the second circuit-patterned layer is located on the second surface; a second bonding material bonding the first top surface to the second circuit-patterned layer; and at least one second spacer employed as supports between the second circuit-patterned layer and the first top surface, wherein a smallest thickness of a portion of the first bonding material in between the first substrate and the first power chip is equal to the first height. 2. The power module of claim 1 , wherein the first spacer is a metal powder sintered structure. 3. The power module of claim 1 , wherein the first spacer is made of a thixotropic material. 4. The power module of claim 1 , wherein the first spacer is a structure by wire bonding technology. 5. The power module of claim 1 , wherein the first spacer is a structure by patterning technology formed on the first circuit-patterned layer. 6. The power module of claim 1 , wherein the first spacer is circular, polygonal, or an intersecting graph in a cross-sectional view. 7. The power module of claim 1 , wherein the first spacer is cylindrical, trapezoidal, arc-shaped, a gradient shape, or a stepped shape in a side view. 8. The power module of claim 1 , wherein the number of the at least one first spacer is two, and the first spacers are adjacent to two opposite edges of the first power chip respectively. 9. The power module of claim 1 , wherein the number of the at least one first spacer is three, and each of the first spacers is adjacent to a corner or an edge of the first power chip. 10. The power module of claim 1 , wherein the number of the at least one first spacer is four, the first power chip has four corners, and the first spacers are respectively adjacent to the corners. 11. The power module of claim 1 , wherein the number of the at least one first spacer is plural, and the first spacers are uniformly distributed underneath the first power chip. 12. The power module of claim 1 , wherein the first top surface has a bonding region and the second spacer is located within the bonding region. 13. The power module of claim 1 , wherein the first top surface has a bonding region, the second spacer is located out of the bonding region, and is made of an insulating material. 14. The power module of claim 1 , wherein the first spacer has four extensions, the first power chip has four corners, and the extensions respectively extend toward the corners. 15. The power module of claim 14 , further comprising: a second power chip located between the first circuit-patterned layer and the second circuit-patterned layer, the second power chip having a second bottom surface and a second top surface; a fourth bonding material bonding the second bottom surface to the first circuit-patterned layer; at least one fourth spacer employed as supports between the first circuit-patterned layer and the second bottom surface; a second shim located between the second circuit-patterned layer and second top surface; a fifth bonding material bonding the second shim to the second circuit-patterned layer; at least one fifth spacer employed as supports between the second circuit-patterned layer and the second shim; a sixth bonding material bonding the second shim to the second top surface; and at least one sixth spacer employed as supports between the second top surface and the second shim. 16. A power module, comprising: a first substrate comprising a first circuit-patterned layer and a first insulating layer, the first insulating layer having a first surface on which the first circuit-patterned layer is located; a first power chip having a first bottom surface and a first top surface; a first bonding material bonding the first power chip to the first circuit-patterned layer and connected to the first bottom surface; at least one first spacer connected to the first bottom surface and employed as supports between the first circuit-patterned layer and the first power chip; a second substrate comprising a second insulating layer and a second circuit-patterned layer, wherein the second insulating layer has a second surface, and the second circuit-patterned layer is located on the second surface; a first shim located between the second circuit-patterned layer and the first top surface; a second bonding material bonding the first shim to the second circuit-patterned layer; at least one second spacer employed as supports between the second circuit-patterned layer and the first shim; a third bonding material bonding the first top surface and the first shim; and at least one third spacer employed as supports between the first top surface and the first shim. 17. The power module of claim 16 , wherein the second spacer has a second height, the third spacer has a third height, the fourth spacer has a fourth height, the fifth spacer has a fifth height, the sixth spacer has a sixth height, the first height is equal to the fourth height, the second height is equal to the fifth height, a thickness of the first shim is equal to a thickness of the second shim, and a difference between a thickness of the first power chip and a thickness of the second power chip is equal to a difference between the third height and the sixth height.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by changes in properties of the die-attach connectors during connecting · CPC title

  • Die-attach connectors · CPC title

  • Package configurations · CPC title

  • Soldering or alloying · CPC title

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Frequently asked questions

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What does patent US10276522B2 cover?
The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-p…
Who is the assignee on this patent?
Delta Electronics Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 30 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).