Stress resistant micro-via structure for flexible circuits

Patent metadata

Field	Value
Publication number	US-10276486-B2
Application number	US-71545010-A
Country	US
Kind code	B2
Filing date	Mar 2, 2010
Priority date	Mar 2, 2010
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.

First claim

What is claimed is:

1. A method of forming a chip package comprising:
providing a silicon wafer having an integrated circuit (IC) thereon and a plurality of die pads formed on a top surface thereof;
applying an adhesive layer to the top surface of the silicon wafer;
adhering the silicon wafer to a free-standing polyimide flex layer by way of the adhesive layer;
forming a plurality of vias through the free-standing polyimide flex layer and the adhesive layer, each of the plurality of vias extending to a respective one of the plurality of die pads; and
forming a plurality of metal interconnects on the free-standing polyimide flex layer such that each of the plurality of metal interconnects extends through a respective via to electrically connect to a respective die pad, wherein forming the plurality of metal interconnects comprises:
determining a desired metal interconnect thickness based on a thickness of the adhesive layer;
depositing a metal material on the free-standing polyimide flex layer and in the plurality of vias having the desired metal interconnect thickness; and
patterning and etching the metal material to form the plurality of metal interconnects having the desired metal interconnect thickness;
wherein upon patterning and etching the metal material to form the plurality of metal interconnects, a void remains within each of the plurality of vias that is free of a metallic material; and
wherein depositing, patterning, and etching each of the plurality of metal interconnects comprises:
forming a cover pad covering a portion of a top surface of the free-standing polyimide flex layer;
forming a sidewall extending down from the cover pad and through a respective via along a perimeter thereof; and
forming a base connected to the sidewall and forming an electrical connection with a respective die pad;
wherein the sidewall and the base are formed to have the determined desired metal interconnect thickness, with the sidewall and the base having an identical thickness that is equal to or greater than a thickness of the adhesive layer; and
wherein forming the cover pad comprises forming a cover pad having a thickness greater than the thickness of the sidewall and base.

2. The method of claim 1 wherein adhering the silicon wafer to the free-standing polyimide flex layer comprises adhering the silicon wafer to the free-standing polyimide flex layer in a face-down orientation.

3. The method of claim 1 wherein applying the adhesive layer comprises applying an adhesive layer having a composition of an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.

4. The method of claim 1 wherein depositing the metal material comprises electroplating the metal material on the free-standing polyimide flex layer and in the plurality of vias.

Assignees

• Gorczyca Thomas Bert
• Saia Richard Joseph
• Mcconnelee Paul Alan
• Gen Electric

Inventors

• Gorczyca Thomas Bert
• Saia Richard Joseph
• Mcconnelee Paul Alan

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/688 Primary

  Flexible insulating substrates · CPC title

• H01L23/4985 Primary

  Electricity · mapped topic

• H01L23/49822

  Electricity · mapped topic