Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-10276476-B1
Application number	US-201815981955-A
Country	US
Kind code	B1
Filing date	May 17, 2018
Priority date	May 17, 2018
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
an interconnection structure disposed on the first surface;
an oxide semiconductor (OS) transistor disposed on the second surface, and the OS transistor comprising a back gate disposed on the second surface of the substrate; and
a contact structure formed between the OS transistor and the interconnection structure, and the contact structure electrically connected to the back gate, wherein the contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.

2. The semiconductor device according to claim 1 , further comprising:
a capacitor disposed on the second surface of the substrate.

3. The semiconductor device according to claim 1 , further comprising:
a capacitor disposed on the first surface of the substrate and located within the interconnection structure.

4. The semiconductor device according to claim 1 , wherein the OS transistor further comprises:
a gate insulator film disposed on the back gate;
an oxide semiconductor (OS) layer disposed on the gate insulator film;
a gate electrode disposed on the OS layer; and
two electrodes disposed on the OS layer and located on two lateral sides of the gate electrode.

5. The semiconductor device according to claim 1 , wherein the interconnection structure comprises a plurality of metal layers, the plurality of metal layers comprise a first metal layer, the first metal layer is most adjacent to the first surface of the substrate among the plurality of metal layers, and the contact structure is electrically connected to the first metal layer.

6. The semiconductor device according to claim 1 , further comprising:
an additional interconnection structure disposed on the second surface of the substrate and electrically connected to the OS transistor; and
an additional contact structure penetrating through the substrate and electrically connecting the additional interconnection structure to the interconnection structure.

7. The semiconductor device according to claim 6 , wherein the additional interconnection structure comprises one layer or two layers of copper metal.

8. The semiconductor device according to claim 1 , further comprising:
a transistor comprising a polysilicon layer disposed on the first surface of the substrate.

9. The semiconductor device according to claim 1 , wherein the contact structure is fully located between a first metal layer of the interconnection structure and the back gate of the OS transistor.

10. The semiconductor device according to claim 1 , further comprising at least a metal interconnect layer formed on the interconnection structure, wherein a plurality of metal layers of the interconnection structure and the metal interconnect layer are different materials.

Assignees

• United Microelectronics Corp

Inventors

• Li Xiang
• Chen Ding-Lung
• Liu en-feng
• Tung Yu-Cheng

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title