Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-10276451-B2
Application number	US-201715679346-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Aug 17, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate; and
a CMOS structure, comprising:
a PMOS structure, comprising:
two first source/drain regions disposed in the substrate;
a first gate dielectric disposed partially in the substrate between the first source/drain regions such that a bottom surface of the first gate dielectric is at a level lower than a top surface of the substrate; and
a fully silicided gate electrode disposed on the first gate dielectric; and

a NMOS structure, comprising:
two second source/drain regions disposed in the substrate;
a second gate dielectric disposed partially in the substrate between the second source/drain regions such that a bottom surface of the second gate dielectric is at a level lower than the top surface of the substrate; and
a non-silicided conductive gate electrode disposed on the second gate dielectric.

2. The semiconductor structure according to claim 1 , wherein the fully silicided gate electrode has a first thickness, the non-silicided conductive gate electrode has a second thickness, and the first thickness is smaller than the second thickness.

3. The semiconductor structure according to claim 2 , wherein the first thickness is smaller than half of the second thickness.

4. The semiconductor structure according to claim 1 , wherein the fully silicided gate electrode is formed of nickel silicide, titanium silicide, or cobalt silicide.

5. The semiconductor structure according to claim 1 , wherein the non-silicided conductive gate electrode is formed of n-type doped polysilicon.

6. The semiconductor structure according to claim 1 , wherein the first gate dielectric and the second gate dielectric are formed of oxide.

7. The semiconductor structure according to claim 1 , wherein the PMOS structure further comprises a n-type well disposed in the substrate, and each of the first source/drain regions comprises:
a p-type doped region disposed in the n-type well;
a heavily p-type doped region disposed in the p-type doped region; and
a p-type silicide region disposed on the heavily p-type doped region.

8. The semiconductor structure according to claim 7 , wherein the PMOS structure further comprises first isolation structures disposed in the p-type doped regions, respectively, and the first isolation structures are disposed at two sides of the first gate dielectric.

9. The semiconductor structure according to claim 1 , wherein the NMOS structure further comprises a p-type well disposed in the substrate, and each of the second source/drain regions comprises:
a n-type doped region disposed in the p-type well;
a heavily n-type doped region disposed in the n-type doped region; and
a n-type silicide region disposed on the heavily n-type doped region.

10. The semiconductor structure according to claim 9 , wherein the NMOS structure further comprises second isolation structures disposed in the n-type doped regions, respectively, and the second isolation structures are disposed at two sides of the second gate dielectric.

Assignees

• United Microelectronics Corp

Inventors

• Li yong-liang
• Su Hao

Classifications

• H10D64/0132

  the conductor being a metallic silicide · CPC title

• H01L29/42376

  Electricity · mapped topic

• H01L27/0928

  Electricity · mapped topic

• H01L21/82385

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic