Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
US-2016210145-A1 · Jul 21, 2016 · US
US10275255B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10275255-B2 |
| Application number | US-201414213135-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 14, 2014 |
| Priority date | Mar 15, 2013 |
| Publication date | Apr 30, 2019 |
| Grant date | Apr 30, 2019 |
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A method for dependency broadcasting through a source organized source view data structure. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source organized source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; upon dispatch of one block of the instruction blocks, broadcasting a number belonging to the one block to a row of the source view data structure that relates that block and marking the sources of the row accordingly; and updating the dependency information of remaining instruction blocks in accordance with the broadcast.
Opening claim text (preview).
What is claimed is: 1. A method for dependency broadcasting through a source organized source view data structure, the method comprising: receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block; the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources; populating a source organized source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by incoming instruction blocks; upon dispatch of one block of the instruction blocks, broadcasting a number belonging to the one block to a row of the source view data structure that relates to the one block and marking sources of the row accordingly; and updating dependency information of remaining instruction blocks in accordance with the broadcast. 2. The method of claim 1 , wherein a register view data structure, the source view data structure and an instruction view data structure comprise a scheduler architecture. 3. The method of claim 1 , wherein information about registers referred to by the instruction blocks is stored in a register view data structure. 4. The method of claim 1 , wherein information about sources referred to by the instruction blocks is stored in the source view data structure. 5. The method of claim 1 , wherein information about instructions referred to by the instruction blocks is stored in an instruction view data structure. 6. The method of claim 1 , wherein the register template comprises data structures storing dependency and inheritance information referred to by the instruction blocks. 7. The method of claim 1 , wherein the source view data structure determines when a particular block can be dispatched wherein the determining comprises checking if a ready bit corresponding to each instruction source of the particular block is set. 8. A computer system having a processor coupled to a memory, wherein the processor is configured to implement a method for dependency broadcasting through a source organized source view data structure, comprising: receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block; the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources; populating a source organized source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by incoming instruction blocks; upon dispatch of one block of the instruction blocks, broadcasting a number belonging to the one block to a row of the source view data structure that relates to the one block and marking sources of the row accordingly; and updating dependency information of remaining instruction blocks in accordance with the broadcast. 9. The computer system of claim 8 , wherein a register view data structure, the source view data structure and an instruction view data structure comprise a scheduler architecture. 10. The computer system of claim 8 , wherein information about registers referred to by the instruction blocks is stored in a register view data structure. 11. The computer system of claim 8 , wherein information about sources referred to by the instruction blocks is stored in the source view data structure. 12. The computer system of claim 8 , wherein information about instructions referred to by the instruction blocks is stored in an instruction view data structure. 13. The computer system of claim 8 , wherein the register template comprises data structures storing dependency and inheritance information referred to by the instruction blocks. 14. The computer system of claim 8 , wherein the source view data structure determines when a particular block can be dispatched wherein the determining comprises checking if a ready bit corresponding to each instruction source of the particular block is set. 15. A computer system having a processor coupled to a memory, the memory having computer readable code which when executed by the computer system causes the computer system to implement a method for dependency broadcasting through a source organized source view data structure, comprising: grouping incoming instructions to form instruction blocks; tracking instruction destinations by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks wherein the tracking comprises an incoming instruction block writing its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block, and wherein further the register template is updated by an arrival of the incoming instruction block; the incoming instruction block reading fields of the register template corresponding to its register sources to retrieve its instruction sources; populating a source organized source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by incoming instruction blocks; upon dispatch of one block of the instruction blocks, broadcasting a number belonging to the one block to a row of the source view data structure that relates to the one block and marking sources of the row accordingly; and updating dependency information of remaining instruction blocks in accordance with the broadcast. 16. The computer system of claim 15 , wherein a register view data structure, the source view data structure and an instruction view data structure comprise a scheduler architecture. 17. The computer system of claim 15 , wherein information about registers referred to by the instruction blocks is stored in a register view data structure. 18. The computer system of claim 15 , wherein information about sources referred to by the instruction blocks is stored in the source view data structure. 19. The computer system of claim 15 , wherein information about instructions referred to by the instruction blocks is stored in an instruction view data structure.
to perform operations for flow control · CPC title
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title
Dependency mechanisms, e.g. register scoreboarding · CPC title
of compound instructions · CPC title
Instruction completion, e.g. retiring, committing or graduating · CPC title
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