Apparatus and method for subtracting significand values of floating-point operands

Patent metadata

Field	Value
Publication number	US-10275218-B1
Application number	US-201715793063-A
Country	US
Kind code	B1
Filing date	Oct 25, 2017
Priority date	Oct 25, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalized difference value.

First claim

The invention claimed is:

1. An apparatus comprising:
input circuitry to provide a first significand value of a first floating-point operand and a second significand value of a second floating-point operand;
significand shift control circuitry to assert a shift signal when a difference is detected between at least one low order bit of a first exponent value of the first floating-point operand and a corresponding at least one low order bit of a second exponent value of the second floating-point operand;
first processing circuitry to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted;
second processing circuitry to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted;
first shift estimation circuitry to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount;
second shift estimation circuitry to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount; and
shifted difference value generation circuitry to produce, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is a non-negative value, and the second difference value left shifted by the second estimated left shift amount when the second difference value is a non-negative value.

2. An apparatus as claimed in claim 1 , wherein the shifted difference value generation circuitry comprises:
selection circuitry to select, as a chosen difference value, one of the first difference value and the second difference value that is a non-negative value; and
left shift circuitry to generate the shifted difference value by shifting the chosen difference value by the first estimated left shift amount when the chosen difference value is the first difference value, and by shifting the chosen difference value by the second estimated left shift amount when the chosen difference value is the second difference value.

3. An apparatus as claimed in claim 1 , wherein:
the first and second exponent values differ at most by one; and
the significand shift control circuitry is arranged to assert the shift signal when a difference is detected between a least significant bit value of the first and second exponent values.

4. An apparatus as claimed in claim 3 , wherein the right-shifted versions of the first and second significand values are formed by right-shifting the first and second significand values, respectively, by one bit position.

5. An apparatus as claimed in claim 1 , wherein the first and second significand values comprise a multi-bit fraction value of the corresponding first and second floating-point operands, and the input circuitry is arranged to provide the first and second significand values to include at least one padding bit to the right of a least significant fraction bit of the multi-bit fraction value.

6. An apparatus as claimed in claim 5 , wherein the fraction value of the second floating-point operand is expressed using more bits than the fraction value of the first floating-point operand, and the input circuitry is arranged to include more padding bits within the first significand value than within the second significand value so that the first and second significand values are expressed using the same number of bits.

7. An apparatus as claimed in claim 6 , wherein the second floating-point operand is an unrounded multiplication result of a previously performed multiplication operation.

8. An apparatus as claimed in claim 1 , wherein the input circuitry is arranged to set a most significant bit of the first significand value to 1 when the first exponent value is non-zero, and is arranged to set a most significant bit of the second significand value to 1 when the second exponent value is non-zero.

9. An apparatus as claimed in claim 1 , wherein each of the first shift estimation circuitry and the second shift estimation circuitry comprise mask generation circuitry to generate one or more masks in parallel with the generation of the estimated left shift amount.

10. An apparatus as claimed in claim 9 , wherein each of the first shift estimation circuitry and the second shift estimation circuitry further comprise:
significand analysis circuitry to generate, from analysis of the significand values subjected to the associated subtraction operation, a first bit string identifying a most significant bit position within the difference value produced by the associated subtraction operation that is predicted to have its bit set to a logic 1 value; and
shift determination circuitry to determine the associated estimated shift amount in dependence on the first bit string;
the mask generation circuitry being arranged to use the first bit string to produce the one or more masks at a same time or before the shift determination circuitry determines the associated estimated shift amount.

11. An apparatus as claimed in claim 10 , wherein each of the first shift estimation circuitry and the second shift estimation circuitry further comprise:
shift limiting circuitry to generate from an exponent value a second bit string identifying a shift limit bit position, the shift limiting circuitry having computation circuitry to perform, for each bit position in at least a subset of bit positions of the second bit string, an associated computation using bits of the exponent value to determine a value for that bit position within the second bit string, the associated computation being different for different bit positions; and
combining circuitry to generate a combined bit string from the first and second bit strings;
the shift determination circuitry being arranged to determine the associated estimated shift amount from the combined bit string.

12. An apparatus as claimed in claim 11 , wherein the shift limiting circuitry within the first shift estimation circuitry is arranged to use the first exponent value and the shift limiting circuitry within the second shift estimation circuitry is arranged to use the second exponent value.

13. An apparatus as claimed in claim 9 , further comprising:
significand overflow detection circuitry to detect, based on said one or more masks, and at least one of the first difference value and the second difference value, an overflow condition where the shifted difference value will overflow; and
shift correction circuitry, responsive to detection of the overflow condition, to perform a corrective shift operation such that the shifted difference value is right-shifted by one bit position.

14. An apparatus as claimed in claim 9 , wherein said one or more masks comprise information used for rounding determination, and the apparatus further comprises:
rounding determination circuitry to set a rounding bit value in dependence on a rounding determination operation performed using the one or more masks; and
rounding circuitry to add the rounding bit value to the shifted difference value.

15. An apparatus as claimed in claim 14 , wherein:
the second floating-point operand is an unrounded multiplicatio

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond

Classifications

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/49952

  Sticky bit · CPC title

• G06F7/4912 Primary

  Adding; Subtracting (G06F7/492, G06F7/498 take precedence) · CPC title