Fast and Autonomous mechanism for CPU OC protection

Patent metadata

Field	Value
Publication number	US-10275010-B2
Application number	US-201515119731-A
Country	US
Kind code	B2
Filing date	Feb 16, 2015
Priority date	Feb 21, 2014
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

First claim

What is claimed is:

1. An apparatus comprising:
a central processing unit (CPU);
a Phase-Locked Loop (PLL) controller that receives a PLL frequency control signal, and in response outputs a PLL clock signal;
a clock-gating controller that receives the PLL clock signal and a frequency dithering control signal, and in response outputs a CPU clock signal; and
an over-current protection (OCP) controller that monitors a CPU total power consumption based on received CPU activity information, and wherein in response to detecting that the CPU power is above a predefined threshold while the CPU clock signal is at a first CPU clock frequency and the PLL clock signal is at a first PLL clock frequency, the OCP controller is operative to:
output the frequency dithering control signal which reduces the first CPU clock frequency while the PLL clock signal is at the first PLL clock frequency; and
output the PLL frequency control signal which reduces the first PLL clock frequency such that the CPU does not reach an over-current limit.

2. The apparatus of claim 1 , wherein the OCP controller comprises a power meter that monitors the CPU total power consumption based on the CPU activity information.

3. The apparatus of claim 2 , wherein the CPU total power consumption includes a dynamic power consumption and a leakage power consumption.

4. The apparatus of claim 1 , wherein the frequency dither control signal controls the clock-gating controller to reduce a clock gating percentage by periodically skipping clock cycles to thereby reduce a ratio of a CPU clock frequency and a PLL clock frequency when the CPU power is above the predefined threshold.

5. The apparatus of claim 4 , wherein the OCP controller outputs the frequency dither control signal after detecting the CPU power is above the predefined threshold for a number of CPU clock cycles.

6. The apparatus of claim 1 , wherein the PLL frequency control signal controls the PLL controller to reduce a PLL clock frequency when the CPU power is above the predefined threshold.

7. The apparatus of claim 6 , wherein the PLL clock frequency is reduced such that a ratio of a CPU clock frequency and the PLL clock frequency is substantially equal to one.

8. The apparatus of claim 1 , further comprising: a power management integrated circuit (PMIC) that supplies a PMIC voltage to the CPU.

9. The apparatus of claim 8 , wherein the OCP controller also outputs a PMIC voltage control signal to the PMIC to control the PMIC voltage in response to the CPU total power consumption and PMIC load information.

10. The apparatus of claim 9 , wherein the PMIC voltage control signal controls the PMIC to reduces the PMIC voltage when the PLL clock frequency is reduced.

11. A method, comprising:
(a) receiving central processing unit (CPU) activity information of a CPU;
(b) generating a phase-locked loop (PLL) frequency control signal that controls a PLL clock frequency of a PLL clock outputted from a PLL controller;
(c) generating a frequency dithering control signal that controls a CPU clock frequency of a CPU clock outputted from a clock-gating controller; and
(d) monitoring a CPU total power consumption based on the received CPU activity information, and in response to detecting that the CPU power is above a predefined threshold while the CPU clock signal is at a first CPU clock frequency and the PLL clock signal is at a first PLL clock frequency, outputs the frequency dithering control signal which reduces the first CPU clock frequency while the PLL clock signal is at the first PLL clock frequency, and outputs the PLL frequency control signal which reduces the first PLL clock frequency such that the CPU does not reach an over-current limit.

12. The method of claim 11 , wherein the monitoring in (d) involves using a power meter to monitor the CPU total power consumption based on the CPU activity information.

13. The method of claim 12 , wherein the CPU total power consumption includes a dynamic power consumption and a leakage power consumption.

14. The method of claim 11 , wherein the frequency dither control signal reduces a clock gating percentage by periodically skipping clock cycles to thereby reduce a ratio of the CPU clock frequency and the PLL clock frequency when the CPU power is above the predefined threshold.

15. The method of claim 14 , wherein the frequency dither control signal is generated after detecting the CPU power is above the predefined threshold for a number of CPU clock cycles.

16. The method of claim 11 , wherein the PLL frequency control signal reduces the PLL clock frequency when the CPU power is above the predefined threshold.

17. The method of claim 16 , wherein the PLL clock frequency is reduced such that a ratio of the CPU clock frequency and the PLL clock frequency is substantially equal to one.

18. The method of claim 11 , further comprising:
monitoring power management integrated circuit (PMIC) load information of a PMIC that supplies a PMIC voltage to the CPU.

19. The method of claim 18 , further comprising:
generating a PMIC voltage control signal to control the PMIC voltage in response to the CPU total power consumption and the PMIC load information.

20. The method of claim 19 , wherein the PMIC voltage control signal controls the PMIC to reduce the PMIC voltage when the PLL clock frequency is reduced.

Assignees

• Mediatek Singapore Pte Ltd
• Mair Hugh Thomas
• Gururajarao Sumanth Katte
• Gammie Gordon
• Wang Alice
• Ko Uming
• Lagerquist Rolf

Inventors

• Mair Hugh Thomas
• Gururajarao Sumanth Katte
• Gammie Gordon
• Wang Alice
• Ko Uming
• Lagerquist Rolf

Classifications

• Y02D10/126

  Cross-Sectional Technologies · mapped topic

• Y02D10/172

  Cross-Sectional Technologies · mapped topic

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title