Current-controlled voltage regulation

Patent metadata

Field	Value
Publication number	US-10274986-B2
Application number	US-201715713215-A
Country	US
Kind code	B2
Filing date	Sep 22, 2017
Priority date	Mar 31, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

An integrated circuit is disclosed for current-controlled voltage regulation. In an example aspect, the integrated circuit includes a voltage regulator and a current-controlled clamp. The voltage regulator has a regulator output node and produces a regulator current. The voltage regulator includes an error amplifier and an output transistor. The error amplifier has first and second input nodes and an error amplifier output node, with the first input node coupled to a reference voltage. The error amplifier generates an error amplifier output voltage at the output node. The output transistor is coupled between the error amplifier output node and the regulator output node. The output transistor is coupled to the second input node via the regulator output node to establish a feedback path for the voltage regulator. The current-controlled clamp is coupled to the error amplifier output node and clamps the error amplifier output voltage based on the regulator current.

First claim

What is claimed is:

1. An apparatus comprising:
a voltage regulator having a regulator output node and configured to produce at least one regulator current, the voltage regulator including:
an error amplifier having a first input node, a second input node, and an error amplifier output node, the first input node coupled to a reference voltage, the error amplifier configured to generate an error amplifier output voltage at the error amplifier output node; and
an output transistor coupled between the error amplifier output node and the regulator output node, the output transistor coupled to the second input node of the error amplifier via the regulator output node to establish a feedback path for the voltage regulator; and

a current-controlled clamp coupled to the error amplifier output node, the current-controlled clamp configured to clamp the error amplifier output voltage based on the at least one regulator current, the current-controlled clamp including a current estimator configured to estimate the at least one regulator current of the voltage regulator to produce an estimated current.

2. The apparatus of claim 1 , wherein:
the voltage regulator includes a buffer coupled between the error amplifier output node and the output transistor, the buffer including at least one branch configured to conduct the at least one regulator current; and
the current estimator includes a current mirror configured to generate the estimated current based on the at least one regulator current.

3. The apparatus of claim 2 , wherein:
the at least one branch includes a branch transistor configured to produce the at least one regulator current flowing through the branch transistor; and
the current mirror comprises part of a parallel circuit arrangement having a mirror transistor that is coupled to the branch transistor such that the mirror transistor is configured to produce the estimated current at a level that substantially replicates that of the at least one regulator current.

4. The apparatus of claim 1 , wherein the current-controlled clamp includes an error amplifier voltage clamp, the error amplifier voltage clamp configured to clamp the error amplifier output voltage based on the estimated current.

5. The apparatus of claim 4 , wherein the error amplifier voltage clamp includes a voltage pulling device configured to adjust the error amplifier output voltage based on the estimated current.

6. The apparatus of claim 5 , wherein the error amplifier voltage clamp includes impedance circuitry coupled to the voltage pulling device.

7. The apparatus of claim 5 , wherein:
the error amplifier voltage clamp includes a difference determiner coupled to the voltage pulling device, the difference determiner configured to generate a current difference indicator based on a regulation current and the estimated current; and
the voltage pulling device is configured to adjust the error amplifier output voltage based on the current difference indicator.

8. The apparatus of claim 7 , wherein:
the error amplifier voltage clamp includes a current source configured to provide the regulation current; and
the regulation current comprises a current level that reproduces the at least one regulator current that flows if the voltage regulator is operating in regulation.

9. The apparatus of claim 1 , wherein the error amplifier comprises an operational amplifier, the operational amplifier configured to generate the error amplifier output voltage based on the reference voltage and a regulator output voltage at the regulator output node.

10. The apparatus of claim 9 , wherein:
the feedback path includes feedback tuning circuitry having a feedback factor and configured to generate a feedback voltage based on the regulator output voltage and the feedback factor; and
the operational amplifier is configured to generate the error amplifier output voltage based on the reference voltage and the feedback voltage.

11. The apparatus of claim 1 , wherein the current-controlled clamp is configured to clamp the error amplifier output voltage so as to retard changes to a regulator output voltage at the regulator output node responsive to changes in a load current drawn by a load coupled to the regulator output node.

12. The apparatus of claim 1 , further comprising:
an integrated circuit, the integrated circuit including the voltage regulator and the current-controlled clamp.

13. The apparatus of claim 12 , wherein:
the integrated circuit includes at least one of logic or memory coupled to the voltage regulator; and
the apparatus includes a screen operably coupled to the integrated circuit.

14. An integrated circuit comprising:
a voltage regulator having a regulator output node and configured to produce at least one regulator current, the voltage regulator including:
an error amplifier having a first input node, a second input node, and an error amplifier output node, the first input node coupled to a reference voltage, the error amplifier configured to generate an error amplifier output voltage at the error amplifier output node based on voltages at the first input node and the second input node; and
an output transistor coupled between the error amplifier output node and the regulator output node, the output transistor coupled to the second input node of the error amplifier via the regulator output node to establish a feedback path for the voltage regulator; and

current-controlled means for clamping the error amplifier output voltage based on the at least one regulator current, the current-controlled means comprising estimation means for estimating the at least one regulator current to produce an estimated current.

15. The integrated circuit of claim 14 , wherein:
the voltage regulator includes a buffer coupled between the error amplifier output node and the output transistor, the buffer configured to conduct the at least one regulator current; and
the estimation means comprises mirror means for mirroring the at least one regulator current of the buffer to produce the estimated current.

16. The integrated circuit of claim 14 , wherein the current-controlled means comprises voltage clamp means for clamping the error amplifier output voltage based on the estimated current, the voltage clamp means coupled to the error amplifier output node.

17. The integrated circuit of claim 16 , wherein the voltage clamp means comprises difference means for determining a current difference indicator based on the estimated current and a regulation current.

18. The integrated circuit of claim 17 , wherein the voltage clamp means comprises voltage means for adjusting the error amplifier output voltage based on the current difference indicator.

19. The integrated circuit of claim 14 , wherein:
the voltage regulator comprises a low-dropout voltage regulator; and
the low-dropout voltage regulator includes feedback means for tuning a feedback factor of the low-dropout voltage regulator.

20. The integrated circuit of claim 14 , further comprising:
a load coupled to the regulator output node, the load configured to draw a load current via the regulator output node intermittently at a relatively low level and a relatively high level,
wherein the current-controlled means is configured to clamp the error amplifier output voltage based on the at least one regulator current so as to reduce a dip of a regulator output voltage at the regulator output node responsive to an onset of the relatively high level of the load current.

21. A method for curren

Assignees

• Qualcomm Inc

Inventors

• Yung Chi Fan
• Zou Xiaodan
• Ho Ngai Yeung
• Guan Hua
• Li Kan

Classifications

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/569

  for protection · CPC title

• G05F1/573

  with overcurrent detector · CPC title

• G05F1/66 Primary

  Regulating electric power · CPC title