Electronic device capable of appropriately using various time displays

Patent metadata

Field	Value
Publication number	US-10274904-B2
Application number	US-201615373423-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Mar 23, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A smart watch includes a main CPU, a sub CPU, a first display unit, and a second display unit. While the main CPU and the sub CPU cooperate with each other and perform a display operation including a time display, time display processing is performed to at least either of the first display unit or the second display unit according to an operation state.

First claim

The invention claimed is:

1. An electronic device, comprising:
a first processor;
a second processor;
a first display unit; and
a second display unit,
wherein:
the first processor and the second processor cooperate with each other and perform a display operation including a time display,
the first processor is selectively set to any of a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, and a pause mode in which a power consumption is lower than the power consumption in the low power mode and the first processor is stopped,
in the normal mode, the first processor performs control such that the first display unit displays a time, and the second processor performs control such that the second display unit does not display a time,
in the low power mode, the second processor performs control such that the first display unit displays a time and the second display unit does not display a time, and
in the pause mode, the first display unit is turned off, and the second processor performs control such that the second display unit displays a time.

2. The electronic device according to claim 1 , further comprising:
a first clock unit configured to count a time by control of the first processor; and
a second clock unit configured to count a time separately from the first clock unit,
wherein:
in the normal mode, the first processor performs control such that the first display unit displays a time counted by the first clock unit,
in the low power mode, the second processor performs control such that the first display unit displays a time counted by the second clock unit, and
in the pause mode, the second processor performs control such that the second display unit displays a time counted by the second clock unit.

3. An electronic comprising:
a first processor;
a second processor;
a first display unit;
a second display unit;
a first clock unit configured to count a time by control of the first processor;
a second clock unit configured to count a time separately from the first clock unit; and
a first counting unit configured to count a predetermined time interval,
wherein:
the first processor and the second processor cooperate with each other and perform a display operation including a time display,
the first processor is selectively set to any of a normal mode, a low power mode in which a power consumption is lower than a power consumption in the normal mode, and a pause mode in which a power consumption is lower than the power consumption in the low power mode and the first processor is stopped,
in the normal mode, the first processor performs control such that the first display unit displays a time counted by the first clock unit at a first time interval which is shorter than the predetermined time interval while updating the time, and the second processor performs control such that the second display unit does not display a time,
in the low power mode, the first processor performs control such that the first display unit displays a time by being called by the first counting unit at the predetermined time intervals, and the second processor performs control such that the second display unit does not display a time, and
in the pause mode, the first display unit is turned off, and the second processor performs control such that the second display unit displays a time counted by the second clock unit.

4. The electronic device according to claim 3 , wherein the second processor operates with low power consumption and/or at a low operation frequency in comparison with the first processor.

5. The electronic device according to claim 4 , wherein the second processor is e selectively set to any of a second normal mode in which the second processor normally operates, and a second low power mode in which the second processor operates with a low power consumption in comparison with the second normal mode.

6. The electronic device according to claim 3 , further comprising a storage unit,
wherein:
the first processor performs control such that the storage unit stores a time counted by the first clock unit and to stop time counting by the first clock unit, in a case in which a power consumption mode is changed from the normal mode to the low power mode, and
when called by the first counting unit in the low power mode, the first processor reads out the time stored in the storage unit, calculates a time in which the predetermined time interval is added to the read out time, and performs control such that the first display unit displays the calculated time.

7. The electronic device according to claim 3 , further comprising a third clock unit configured to count a time separately from the first and second clock units,
wherein, in the low power mode, the first processor stops performs control to stop time counting by the first clock unit, and when called by the first counting unit, the first processor acquires a time from the third clock unit and performs control such that the first display unit displays the time.

8. The electronic device according to claim 7 , wherein when the power consumption mode is changed from the normal mode to the low power mode or the pause mode, the first processor corrects a time of the third clock unit based on a time counted by the first clock unit.

9. The electronic device according to claim 3 , wherein:
the second processor is selectively set to any of a second normal mode in which the second processor normally operates, and a second low power mode in which the second processor operates with low power consumption in comparison with the second normal mode,
the second processor comprises a second counting unit configured to count a second time interval,
the second clock unit is a real time clock, and
the second processor obtains a time of the second clock unit by being called at the second time intervals by the second counting unit, and in the second low power mode, the second time interval is set longer than a time counting interval in the second normal mode.

10. The electronic device according to claim 3 , further comprising a time acquisition unit configured to acquire time information from outside,
wherein the first processor corrects a time counted by the first clock unit based on a time acquired by the time acquisition unit.

11. The electronic device according to claim 10 , wherein when a power consumption mode is changed from the low power mode or the pause mode to the normal mode, the first processor performs control such that the time acquisition unit acquires a time and the first processor corrects a time counted by the first clock unit based on the acquired time.

12. The electronic device according to claim 3 , wherein when the power consumption mode is changed from the normal mode to the low power mode or the pause mode, the first processor corrects a time of the second clock unit based on a time counted by the first clock unit.

13. The electronic device according to claim 3 , wherein:
the second display unit is stacked on an upper portion of the first display unit, and
in the low power mode and the pause mode, in which the second display unit does not display a time, the second display unit is controlled so as to transmit a display content of the first display unit.

14. A display control method for an electronic device, the electronic device including a first processor, a second processor, a first display unit, a second display unit, a first clock unit configured to count a time by control of the first processor, a second clock unit configured to count a time separately from the first clock unit, and a first

Assignees

• Casio Computer Co Ltd

Inventors

• Minami Tsuyoshi
• Mizuno Kimiyasu
• Suzuki Hideo
• Suenaga Takashi
• Nomura Keiichi
• Uchida Shuhei
• Seo Munetaka

Classifications

• G04G19/06 Primary

  Regulation · CPC title

• Y02D10/153

  Cross-Sectional Technologies · mapped topic

• G06F3/147

  using display panels · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G06F1/3265 Primary

  Power saving in display device · CPC title