Collusion attack prevention
US-2024362739-A1 · Oct 31, 2024 · US
US10271051B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10271051-B2 |
| Application number | US-201515515843-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 24, 2015 |
| Priority date | Oct 3, 2014 |
| Publication date | Apr 23, 2019 |
| Grant date | Apr 23, 2019 |
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A method implemented by a processor for coding a real signal, for example an image signal, into a quantized signal, comprises the following steps applied to each real sample of the real signal: converting the real sample into a digital representation, selecting, in the fractional part of the number, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance P i with respect to the neighboring selected non-zero significant bit of higher rank or, for the first non-zero significant bit selected, with respect to the decimal point, deducting from the distance P i the minimum value of distance between two non-zero bits, coding the modified distance P i on a predetermined number M i of bits.
Opening claim text (preview).
The invention claimed is: 1. A computer-implemented method for coding a real signal, for example an image signal, into a quantized signal, said method comprising the following steps applied to each real sample of said real signal: converting, with a processor, the real sample into a binarized sample comprising a fractional part that comprises a digital representation, selecting, with the processor, in the fractional part of the binarized sample, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining, with the processor, its distance P i to a neighboring selected non-zero significant bit of higher rank or, for a first non-zero significant bit selected, to a decimal point, subtracting, with a processor, from said distance P i a minimum value of distance between two non-zero bits in any binarized number converted from any real number according to said digital representation, to obtain a modified distance, coding, with a processor, the modified distance P i on a predetermined number M i of bits. 2. The method for coding a real signal into a quantized signal of claim 1 , comprising a prior step of transforming the real sample into a real number lying strictly between −1 and 1. 3. The method for coding a real signal into a quantized signal of claim 1 , wherein the digital representation is a binary representation. 4. The method for coding a real signal into a quantized signal of claim 1 , wherein the digital representation is a balanced ternary representation in which a +/− sign is associated with each bit of the binarized number, said sign being coded by an additional bit in the quantized signal. 5. The method for coding a real signal into a quantized signal of claim 3 , wherein the minimum value of distance between two non-zero bits is equal to one. 6. The method for coding a real signal into a quantized signal of claim 1 , wherein the digital representation is a canonical signed binary representation which satisfies the following properties: two consecutive bits of the canonical signed binary representation of a number are never simultaneously non-zero, the canonical signed binary representation of a number is unique, the canonical signed binary representation of a number comprises a minimum number of non-zero bits. 7. The method for coding a real signal into a quantized signal of claim 6 , wherein the minimum value of distance between two non-zero bits is equal to two. 8. The method for coding a real signal into a quantized signal of claim 1 , further comprising the steps of: decomposing the value of the modified distance into a sum of 2 M i −1 and of a residual value P′ i+1 if the modified distance P i , associated with the non-zero significant bit of index i, has a value greater than or equal to 2 M i −1, where M i is the number of bits chosen to code the modified distance P i , coding the term 2 M i −1 on the number of bits M i chosen to code the modified distance P i , performing the following substitutions: P N =P N−1 , . . . , P i+2 =P i+1 , P i+1 =P′ i+1 . 9. The method for coding a real signal into a quantized signal according to claim 1 , wherein the real signal is an image signal or a signal composed of synaptic weights of a neural network. 10. A device for coding a real signal, for example a video signal, into a quantized signal, comprising a calculator configured to execute a computer-implemented method for coding a real signal, for example an image signal, into a quantized signal, said method comprising the following steps applied to each real sample of said real signal: converting the real sample into a binarized sample comprising a fractional part that comprises a digital representation, selecting, in the fractional part of the binarized sample, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance P i to a neighboring selected non-zero significant bit of higher rank or, for a first non-zero significant bit selected, to a decimal point, subtracting from said distance P i a minimum value of distance between two non-zero bits in any binarized number converted from any real number according to said digital representation, to obtain a modified distance, coding the modified distance P i on a predetermined number M i of bits. 11. A computer program comprising instructions stored on a tangible non-transitory storage medium for executing on a processor a computer-implemented method for coding a real signal, for example an image signal, into a quantized signal, said method comprising the following steps applied to each real sample of said real signal: converting the real sample into a binarized sample comprising a fractional part that comprises a digital representation, selecting, in the fractional part of the binarized sample, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance P i to a neighboring selected non-zero significant bit of higher rank or, for a first non-zero significant bit selected, to a decimal point, subtracting from said distance P i a minimum value of distance between two non-zero bits in any binarized number converted from any real number according to said digital representation, to obtain a modified distance, coding the modified distance P i on a predetermined number M i of bits. 12. A multiplier circuit configured to calculate the result of multiplying a first number x i by a second number w i , both of which are quantized by applying a computer-implemented method for coding a real signal, for example an image signal, into a quantized signal, said method comprising the following steps applied to each real sample of said real signal: converting the real sample into a binarized sample comprising a fractional part that comprises a digital representation, selecting, in the fractional part of the binarized sample, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance P i to a neighboring selected non-zero significant bit of higher rank or, for a first non-zero significant bit selected, to a decimal point, subtracting from said distance P i a minimum value of distance between two non-zero bits in any binarized number converted from any real number according to said digital representation, to obtain a modified distance, coding the modified distance P i on a predetermined number M i of bits with a number N, equal to two, of distances, said circuit comprising an adder designed to add together the first distance of the first quantized number x i and the first distance of the second quantized number w i , a correspondence table indexed at least by the values of the second distance of the first quantized number x i and of the second distance of the second quantized number w i and a shift register configured to carry out a binary shift on the output of the correspondence table of a number of bits equal to the output of the adder. 13. The multiplier circuit of claim 12 , wherein the correspondence table is furthermore indexed by the sign of the second distance of the first quantized number xi and the sign of the second distance of the second quantized number wi, said multiplier circuit furthermore comprising an exclusive OR logic gate receiving as input the sign of the first distance of the first quantized number xi and the sign of the first distance of the second quantized number wi. 14. A co
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