Apparatus and method for frequency tripling

Patent metadata

Field	Value
Publication number	US-10270456-B1
Application number	US-201815859827-A
Country	US
Kind code	B1
Filing date	Jan 2, 2018
Priority date	Jan 2, 2018
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

First claim

What is claimed is:

1. An apparatus comprising:
a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and
a summing network configured to receive the six-phase signal and output a two-phase signal,
wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

2. The apparatus of claim 1 , wherein the phase interpolator includes six weighted sum circuits, wherein each of the six weighted sum circuits is configured to output a respective phase of the six-phase signal based on a respective weighted sum of a respective pair of phases of the four-phase signal.

3. The apparatus of claim 2 , wherein the six weighted sum circuits include:
a first weighted sum circuit configured to output the first phase of the six-phase signal in accordance with a weighted sum of a first phase and a second phase of the four-phase signal;
a second weighted sum circuit configured to output the second phase of the six-phase signal in accordance with a weighted sum of the second phase and a third phase of the four-phase signal;
a third weighted sum circuit configured to output the third phase of the six-phase signal in accordance with a weighted sum of the third phase and the second phase of the four-phase signal;
a fourth weighted sum circuit configured to output the fourth phase of the six-phase signal in accordance with a weighted sum of the third phase and a fourth phase of the four-phase signal;
a fifth weighted sum circuit configured to output the fifth phase of the six-phase signal in accordance with a weighted sum of the fourth phase and the first phase of the four-phase signal; and
a sixth weighted sum circuit configured to output a sixth phase of the six-phase signal in accordance with a weighted sum of the first phase and the fourth phase of the four-phase signal.

4. The apparatus of claim 1 , wherein the summing network includes:
a first differential pair configured to receive the first phase and the fourth phase of the six-phase signal and output a first current and a fourth current to a first output node and a second output node, respectively;
a second differential pair configured to receive the third phase and the sixth phase of the six-phase signal and output a third current and a sixth current to the first output node and the second output node, respective;
a third differential pair configured to receive the fifth phase and the second phase of the six-phase signal and output a fifth current and a second current to the first output node and the second node, respectively;
a load network configured to provide a termination to the first output node and the second output node to establish the second phase and the first phase of the two-phase signal, respectively.

5. The apparatus of claim 4 , wherein the load network is a resonator tuned to a third harmonic of the six-phase signal.

6. The apparatus of claim 1 further including a quadrature generation network configured to receive an input clock and output the four-phase signal.

7. The apparatus of claim 6 , wherein the quadrature generation network includes:
a first divide-by-two circuit configured to receive the input clock and output a first phase and a third phase of the four-phase signal, and
a second divide-by-two circuit configured to receive an inversion of the input clock and output a second phase and a fourth phase of the four-phase signal.

8. The apparatus of claim 7 , wherein the first divide-by-two circuit includes a first data flip flop, while the second divide-by-two circuit includes a second data flip flop.

9. A method for frequency tripling comprising:
receiving an input clock;
generating a four-phase signal from the input clock using a quadrature generation network;
generating a six-phase signal from the four-phase signal using interpolation;
summing a first phase, a third phase, and a fifth phase of the six-phase signal to generate a second phase of a two-phase signal;
summing a second phase, a fourth phase, and a sixth phase of the six-phase signal to generate a first phase of the two-phase signal; and
filtering the two-phase signal to extract a third harmonic component,
wherein the extracted third harmonic component is three times the frequency of the input clock.

10. The method of claim 9 , wherein the quadrature generation network includes a first divide-by-two circuit configured to receive the input clock and output a first phase and a third phase of the four-phase signal, and a second divide-by-two circuit configured to receive an inversion of the input clock and output a second phase and a fourth phase of the four-phase signal.

11. The method of claim 10 , wherein the first divide-by-two circuit includes a first data flip flop, while the second divide-by-two circuit includes a second data flip flop.

12. The method of claim 9 , wherein each of the six phases of the six-phase signal is interpolated from a respective pair of phases of the four-phase signal.

13. The method of claim 12 , wherein the first phase of the six-phase signal is interpolated from a first phase and a second phase of the four-phase signal, the second phase of the six-phase signal is interpolated from the second phase and a third phase of the four-phase signal, the third phase of the six-phase signal is interpolated from the third phase and the second phase of the four-phase signal, the fourth phase of the six-phase signal is interpolated from the third phase and the fourth phase of the four-phase signal, the fifth phase of the six-phase signal is interpolated from the fourth phase and the first phase of the four-phase signal, and the sixth phase of the six-phase signal is interpolated from the first phase and the fourth phase of the four-phase signal.

14. The method of claim 9 , wherein a weighted sum is used to embody interpolation.

15. The method of claim 14 , wherein each of the six phases of the six-phase signal is generated by a respective weighted sum of a respective pair of phases of the four-phase signal.

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Chia-Liang (Leon)
• Xu Wenbo
• Song Fei

Classifications

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/1806

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H04L27/148

  using filters, including PLL-type filters · CPC title

• H03L7/0998 Primary

  using phase interpolation · CPC title