Buffer circuit

Patent metadata

Field	Value
Publication number	US-10270446-B2
Application number	US-201715481584-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 7, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A buffer circuit receives a working supply voltage which may vary within a voltage range. The buffer circuit has a high voltage constant current buffer circuit, and in this circuit, the source of the first NMOS transistor is grounded, and drains of the first NMOS transistor and the first PMOS transistor are connected. The source of the second PMOS transistor is connected to the supply voltage input of the buffer circuit, and the drain of the second PMOS transistor is connected to the source of the first PMOS transistor. The input end of the high voltage diode connected composite transistors is connected to the supply voltage input of the buffer circuit, and the output end of the diode connected transistors is connected to the gates of first and second PMOS transistors. The first PMOS and NMOS transistors are high-voltage transistors. The second PMOS transistor is a low-voltage transistor.

First claim

What is claimed is:

1. A buffer circuit, operating at a working voltage received by its input end, wherein the working voltage is controlled within a voltage range, the buffer circuit comprising:
a high voltage constant current buffer circuit, comprising:
a first PMOS transistor and a first NMOS transistor, the source of the first NMOS transistor being grounded, and the drain of the first PMOS transistor connecting to the drain of the first NMOS transistor and an output end of the buffer circuit;

a second PMOS transistor, the source of the second PMOS transistor connecting to the supply voltage of the high voltage constant current buffer circuit, and the drain of the second PMOS transistor connecting to the source of the first PMOS transistor; and
a high voltage diode connected composite transistors, an input end of the high voltage diode connected composite transistors connecting to the supply voltage of the high voltage constant current buffer circuit, an output end of the high voltage diode connected composite transistors connecting to the gate of the first PMOS transistor and the gate of the second PMOS transistor;
wherein the second PMOS transistor in the high voltage constant current buffer circuit is a low-voltage PMOS transistor, the first PMOS transistor in the high voltage constant current buffer circuit is a high-voltage PMOS transistor, and the first NMOS transistor in the high voltage constant current buffer circuit is a high-voltage NMOS transistor, to reduce the variation of an output current of the buffer circuit resulting from changes of the supply voltage.

2. The buffer circuit according to claim 1 , wherein the high voltage diode connected composite transistors comprises:
a fourth PMOS transistor and a fifth PMOS transistor, the source of the fourth PMOS transistor is an input end of the high voltage diode connected composite transistors, the drain of the fifth PMOS transistor is an output end of the high voltage diode connected composite transistors, the drain of the fourth PMOS transistor connecting to the source of the fifth PMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor and the output end of the high voltage diode connected composite transistors being connected.

3. The buffer circuit according to claim 2 , wherein the fourth PMOS transistor in the high voltage diode connected composite transistors is a low-voltage PMOS transistor, and the fifth PMOS transistor in the composite diode connected transistors is a high-voltage PMOS transistor.

4. The buffer circuit according to claim 3 , further comprising:
a resistor, the resistor connecting to the output end of the high voltage diode connected composite transistors, and the gate of the first PMOS transistor and the gate of the second PMOS transistor.

5. The buffer circuit according to claim 1 , further comprising:
a current boosting circuit, connecting to the high voltage constant current buffer circuit and a pulse generator, and receiving a switch signal from the pulse generator;
wherein the pulse generator outputs a narrow pulse signal to turn on the second NMOS transistor to drive a PMOS current mirror of the current boosting circuit, and the current mirror directly outputs the current to boost the output current of the high voltage constant current buffer circuit;
wherein the pulse generator outputs the narrow pulse signal to the current boosting circuit when an input signal of the pulse generator transits from low to high, and the current boosting circuit boosts and then outputs the received output current of the high voltage constant current buffer circuit.

6. The buffer circuit according to claim 5 , wherein the current boosting circuit comprises:
a PMOS current mirror;
a second NMOS transistor, the drain of the second NMOS transistor connecting to the PMOS current mirror, and the gate of the second NMOS transistor connecting to the pulse generator; and
a third NMOS transistor, the drain of the third NMOS transistor connecting to source of the second NMOS transistor, the source of the third NMOS transistor being grounded, and the gate of the third NMOS transistor receiving a buffer bias voltage;
wherein the pulse generator outputs the switch narrow pulse signal to the second NMOS transistor to turn on the second NMOS transistor when the input signal of the pulse generator transits from low to high, such that the third NMOS transistor provides an extra current to the PMOS current mirror to boost the output current received by the high voltage constant current buffer circuit from the current boosting circuit, and then the boosted current is outputted from the high voltage constant current buffer circuit.

7. The buffer circuit according to claim 6 , wherein the second NMOS transistor is a high-voltage NMOS transistor.

8. The buffer circuit according to claim 6 , wherein the PMOS current mirror comprises a sixth PMOS transistor and a seventh PMOS transistor, the gate of the sixth PMOS transistor connecting to the gate of the seventh PMOS transistor, the source of the sixth PMOS transistor and the source of the seventh PMOS transistor both connecting to the supply voltage input of the buffer circuit, and gates and drains of the sixth PMOS transistor and the seventh PMOS transistor all connecting to drain of the second NMOS transistor.

9. The buffer circuit according to claim 6 , wherein the sixth PMOS transistor is a low-voltage PMOS transistor and the seventh PMOS transistor is a high-voltage PMOS transistor.

10. The buffer circuit according to claim 1 , wherein the voltage range is from 4.5V to 30V.

Assignees

• Lite On Singapore Pte Ltd

Inventors

• Tan Meng-Tong
• Lim Huey-Jen
• Wang You-Fa

Classifications

• H03K19/017536 Primary

  using opto-electronic devices · CPC title