Input output for an integrated circuit

Patent metadata

Field	Value
Publication number	US-10269772-B2
Application number	US-201715702610-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Dec 6, 2013
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers of the three-dimensional integrated circuit. The input output circuit has first and second input output circuitry, wherein the first input output circuitry operates faster than the second input output circuitry.

First claim

What is claimed is:

1. A three-dimensional integrated circuit having a plurality of layers disposed in a stacked relationship, comprising:
logic circuitry having one or more transistors and embodied in a first layer of said three-dimensional integrated circuit;
an input output circuit electrically coupled to said logic circuitry and having a plurality of transistors embodied in at least two layers of said three-dimensional integrated circuit, said input output circuit comprising:
first input output circuitry adapted to operate at a first speed, and
second input output circuitry adapted to operate at a second speed that is slower than said first speed.

2. The three-dimensional integrated circuit of claim 1 , wherein said first input output circuitry includes a plurality of transistors embodied in said first layer.

3. The three-dimensional integrated circuit of claim 2 , wherein said first input output circuitry comprises a first receiver circuit, a first level shifter circuit, and a first pre-driver circuit.

4. The three-dimensional integrated circuit of claim 1 , wherein said plurality of layers comprises said first layer, a second layer and a third layer; said first input output circuitry includes a plurality of transistors embodied in said third layer; and said second input output circuitry includes a plurality of transistors embodied in said second layer.

5. The three-dimensional integrated circuit of claim 4 , wherein said first input output circuitry further includes a plurality of transistors embodied in said first layer.

6. The three-dimensional integrated circuit of claim 4 , wherein said plurality of transistors of said first input output circuitry embodied in said third layer comprise a first post-driver and a first electrostatic discharge protection circuit; and said plurality of transistors of said second input output circuitry embodied in said second layer comprise a second post-driver and a second electrostatic discharge protection circuit.

7. The three-dimensional integrated circuit of claim 1 , further comprising
a first plurality of connection pads disposed on an external surface of said three-dimensional integrated circuit and coupled to said first input output circuitry to provide connectivity at said first speed;
a second plurality of connection pads on said external surface of said three-dimensional integrated circuit and coupled to said second input output circuitry to provide connectivity at said second speed; and
wherein said first plurality of connection pads is disposed along a peripheral area of said external surface outward of said second plurality of connection pads.

8. The three-dimensional integrated circuit of claim 7 , wherein said plurality of layers comprises said first layer, a second layer and a third layer; said first input output circuitry includes a plurality of transistors embodied in said third layer coupled to said first plurality of connection pads; and said second input output circuitry includes a plurality of transistors embodied in said second layer coupled to said second plurality of connection pads.

9. The three-dimensional integrated circuit of claim 1 , wherein said logic circuitry embodied in said first layer is adapted to operate between a first ground level and a first power level; and wherein said input output circuitry includes one or more transistors embodied in said second layer that are adapted to operate between a second ground level and a second power level different from said first power level; and further comprising:
a power and ground distribution network including a mesh embodied in said first layer adapted to provide said first power level to said logic circuitry and a ring embodied in said second layer adapted to provide said second power level to said input output circuitry embodied in said second layer.

10. A method of using a three-dimensional integrated circuit having a plurality of layers disposed in a stacked relationship, wherein logic circuitry having one or more transistors is embodied in a first layer of said three-dimensional integrated circuit, an input output circuit electrically coupled to said logic circuitry has a plurality of transistors embodied in at least two layers of said three-dimensional integrated circuit, said input output circuit comprising first input output circuitry adapted to operate at a first speed, and second input output circuitry adapted to operate at a second speed that is slower than said first speed, the method comprising:
providing electrical power to said three-dimensional integrated circuit;
generating a first signal in said logic circuitry embodied in said first layer of said three-dimensional integrated circuit;
providing said first signal to said first input output circuitry of said three-dimensional integrated circuit;
outputting, at said first speed, said first signal from said input output circuitry to a component external to said three-dimensional integrated circuit;
receiving and processing said first signal in said external component;
generating a second signal in said logic circuitry embodied in said first layer of said three-dimensional integrated circuit;
providing said second signal to said second input output circuitry of said three-dimensional integrated circuit;
outputting, at said second speed, said second signal from said second input output circuitry; and
receiving and processing said second signal external to said three-dimensional integrated circuit.

11. The method of claim 10 , wherein said first input output circuitry includes a plurality of transistors embodied in said first layer.

12. The method of claim 11 , wherein said first input output circuitry comprises a first receiver circuit, a first level shifter circuit, and a first pre-driver circuit.

13. The method of claim 10 , wherein said plurality of layers comprises said first layer, a second layer and a third layer; said first input output circuitry includes a plurality of transistors embodied in said third layer; and said second input output circuitry includes a plurality of transistors embodied in said second layer.

14. The method of claim 13 , wherein said first input output circuitry further includes a plurality of transistors embodied in said first layer.

15. The method of claim 13 , wherein said plurality of transistors of said first input output circuitry embodied in said third layer comprise a first post-driver and a first electrostatic discharge protection circuit; and said plurality of transistors of said second input output circuitry embodied in said second layer comprise a second post-driver and a second electrostatic discharge protection circuit.

16. The method of claim 10 , further comprising
providing, by a first plurality of connection pads, connectivity to said first input output circuitry at said first speed, said first plurality of connection pads disposed on an external surface of said three-dimensional integrated circuit;
providing, by a second plurality of connection pads, connectivity to said second input output circuitry at said second speed, said second plurality of connection pads disposed on said external surface of said three-dimensional integrated circuit; and
wherein said first plurality of connection pads is disposed along a peripheral area of said external surface outward of said second plurality of connection pads.

17. The method of claim 16 , wherein said plurality of layers comprises said first layer, a second layer and a third layer; said first input output circuitry includes a plurality of transistors embodied in said third layer coupled to

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fu Chin-Ming

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title