Wrap-around contact on FinFET

Patent metadata

Field	Value
Publication number	US-10269649-B2
Application number	US-201815938225-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Apr 21, 2014
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a neighboring pair of fin structures on a substrate, the fin structures each comprising an epitaxial region extending above an isolation region disposed between the fin structures;
conformally forming a first etch stop layer over the fin structures and the isolation region;
forming a second etch stop layer on the first etch stop layer and on upper surfaces of the epitaxial regions, the second etch stop layer merging between the fin structures, the merging of the second etch stop layer forming an enclosed void between the fin structures;
removing a portion of the first etch stop layer from under-surfaces of the epitaxial regions; and
forming first contacts on portions of the upper surfaces of the epitaxial regions and second contacts on portions of the under-surfaces of the epitaxial regions, wherein the first contacts are a first type of contact and the second contacts are a second type of contact different from the first type of contact.

2. The method of claim 1 , wherein forming the first contacts comprises forming a metal-semiconductor compound layer on the upper surfaces of the epitaxial regions and forming a first metal layer over the metal-semiconductor compound layer, wherein a portion of the under-surfaces of the epitaxial regions is free of the metal-semiconductor compound layer.

3. The method of claim 1 , wherein forming the second contacts comprises forming a dielectric layer on the under-surfaces of the epitaxial regions, wherein a portion of the upper surfaces of the epitaxial regions is free of the dielectric layer.

4. The method of claim 1 , wherein forming the first contacts and forming the second contacts comprises forming a barrier layer over the under-surfaces of the epitaxial regions and over the upper surfaces of the epitaxial regions.

5. The method of claim 1 , wherein forming the first contacts and forming the second contacts comprises forming a second metal layer over the under-surfaces of the epitaxial regions and over the upper surfaces of the epitaxial regions.

6. The method of claim 1 , further comprising removing a portion of the second etch stop layer from the upper surfaces of the epitaxial regions.

7. A method comprising:
forming a semiconductor fin over a substrate;
forming a gate structure over the semiconductor fin;
forming an epitaxial region over the semiconductor fin and adjacent the gate structure, wherein the epitaxial region comprises an upper surface and a lower surface, wherein the upper surface is farther from the substrate than the lower surface;
forming a first contact structure on the lower surface of the epitaxial region, comprising:
forming a dielectric layer over and physically contacting the lower surface; and
forming a first portion of a first metal layer over the dielectric layer; and

forming a second contact structure on the upper surface of the epitaxial region, comprising:
forming a metal-semiconductor compound layer over and physically contacting the upper surface;
forming a second metal layer over the metal-semiconductor compound layer; and
forming a second portion of the first metal layer over the second metal layer.

8. The method of claim 7 , further comprising:
conformally forming a first etch stop layer over the epitaxial region, wherein a first portion of the first etch stop layer extends over the upper surface and a second portion of the first etch stop layer extends over the lower surface; and
forming a second etch stop layer over the first portion of the first etch stop layer, wherein the second portion of the first etch stop layer is free of the second etch stop layer.

9. The method of claim 8 , wherein the epitaxial region is a first epitaxial region of a plurality of epitaxial regions, and wherein the second etch stop layer extends from over the first epitaxial region to over a second epitaxial region that is adjacent the first epitaxial region.

10. The method of claim 9 , wherein forming the second etch stop layer forms an enclosed void disposed between the first epitaxial region and the second epitaxial region.

11. The method of claim 7 , further comprising forming a barrier layer extending over the dielectric layer and over the second metal layer, wherein the first metal layer is disposed over the barrier layer.

12. The method of claim 7 , wherein the metal-semiconductor compound layer comprises a silicide.

13. A method comprising:
forming a first fin structure comprising a fin extending from a substrate and an epitaxial region over the fin;
forming a conformal dielectric layer over the epitaxial region, a first portion of the dielectric layer extending above an upper surface of the epitaxial region and a second portion of the dielectric layer extending under an under-surface of the epitaxial region;
selectively forming a first metal layer above the first portion of the dielectric layer without forming the first metal layer under the second portion of the dielectric layer;
performing an annealing process on the first portion of the dielectric layer, the first metal layer, and the epitaxial region to convert the first portion of the dielectric layer into a metal-semiconductor compound layer; and
forming a conformal barrier layer extending over the first metal layer and the second portion of the dielectric layer.

14. The method of claim 13 , further comprising:
forming a second fin structure adjacent the first fin structure and separated from the first fin structure by an isolation region;
forming a first etch stop layer extending continuously over the first fin structure, over the isolation region, and over the second fin structure; and
forming a second etch stop layer extending from a top surface of the first fin structure to a top surface of the second fin structure, the second etch stop layer extending above the isolation region, wherein a void extends from the first etch stop layer over the isolation region to the second etch stop layer above the isolation region.

15. The method of claim 14 , further comprising removing a portion of the first etch stop layer over the first fin structure.

16. The method of claim 13 , further comprising forming a conductive material over the conformal barrier layer.

17. The method of claim 13 , wherein the conformal barrier layer, the second portion of the dielectric layer, and the under-surface of the epitaxial region form a metal-insulator-semiconductor contact.

18. The method of claim 13 , wherein the dielectric layer comprises a metal oxide.

19. The method of claim 13 , wherein the metal-semiconductor compound layer comprises TiSiGe.

20. The method of claim 13 , wherein the conformal barrier layer comprises TiO 2 .

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H01L29/0653

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L21/823475

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L2029/7858

  Electricity · mapped topic