Method for manufacturing SiC epitaxial wafer and SiC epitaxial wafer

Patent metadata

Field	Value
Publication number	US-10269554-B2
Application number	US-201515329363-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jul 28, 2014
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.

First claim

The invention claimed is:

1. A method for manufacturing a SiC epitaxial wafer which is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on a SiC single crystal substrate having an off angle, the method comprising:
a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and
a final polishing step for further polishing for finish,
wherein the polishing for finish is performed by a grinding process in which a rotational axis of a polishing grindstone is inclined in a tangential direction of an outer circumference of the SiC single crystal substrate to be polished, with respect to a rotational axis of the SiC single crystal substrate to be polished, and
a machined surface roughness (Ra) after performing the final polishing step is from 1 nm to 50 nm.

2. The method for manufacturing a SiC epitaxial wafer according to claim 1 , wherein the final polishing step is performed by inclining the rotational axis of the polishing grindstone by 1° to 45° in the tangential direction of the outer circumference of the SiC single crystal substrate to be polished, with respect to the rotational axis of the SiC single crystal substrate to be polished.

3. The method for manufacturing a SiC epitaxial wafer according to claim 1 , wherein the final polishing step is performed using a resin-bonded grinding stone.

4. The method for manufacturing a SiC epitaxial wafer according to claim 1 , wherein a polishing abrasive grain used in the final polishing step has a grain size of #2,000 to #5,000.

5. The method for manufacturing a SiC epitaxial wafer according to claim 1 , wherein the rough polishing step is performed using a metal bonded grinding stone.

6. The method for manufacturing a SiC epitaxial wafer according to claim 1 , wherein a polishing abrasive grain used in the rough polishing step has a grain size of #400 to #1,500.

7. A SiC epitaxial wafer which is a SiC epitaxial wafer obtained by forming a SiC epitaxial layer on a SiC single crystal substrate having an off angle,
wherein the number of edge defects within a range of 1 mm from an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate is not more than 30 defects/m,
wherein the edge defects are observed as irregularities with a shape in which a flat surface different from the peripheral surface is present in a straight line, and
wherein a machined surface roughness (Ra) of the outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate is from 1 nm to 50 nm.

Assignees

• Showa Denko Kk

Inventors

• Sasaki Yuzo
• Sugano Susumu

Classifications

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2904

  Silicon carbide · CPC title

• H10P14/38

  characterised by treatments done after the formation of the materials · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title