Technologies for network application programming with field-programmable gate arrays

Patent metadata

Field	Value
Publication number	US-10268464-B2
Application number	US-201715644150-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Jul 7, 2017
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A computing device for network application programming, the computing device comprising:
one or more processors; and
one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the computing device to:
analyze a network application source program, wherein the network application source program comprises a declarative description of a network application in a domain-specific language, wherein to analyze the network application source program comprises to generate a parse graph that includes a plurality of nodes based on the network application source program;
translate the declarative description of the network application into a register-transfer level description of the network application, wherein to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate a plurality of TCAM-SRAM structures, wherein each TCAM-SRAM structure corresponds to a node of the parse graph; and
compile the register-transfer level description of the network application into a bitstream definition of the network application, wherein the bitstream is targeted to a field-programmable gate array, wherein to compile the register-transfer level description of the network application into the bitstream definition comprises to optimize a first TCAM-SRAM structure of the plurality of TCAM-SRAM structures by replacing the first TCAM-SRAM structure with a state machine comparison logic.

2. The computing device of claim 1 , wherein the plurality of instructions, when executed, further cause the computing device to program the field-programmable gate array with the bitstream definition in response to compilation of the register-transfer level description.

3. The computing device of claim 1 , wherein the plurality of instructions, when executed, further cause the computing device to partially reconfigure the field-programmable gate array with the bitstream definition in response to compilation of the register-transfer level description.

4. The computing device of claim 3 , wherein:
the plurality of instructions, when executed, further cause the computing device to switch from an active block of the field-programmable gate array to a backup block of the field-programmable gate array in response to partial reconfiguration of the field-programmable gate array; and
to partially reconfigure the field-programmable gate array comprises to program the backup block with the bitstream definition.

5. The computing device of claim 1 , wherein to compile the register-transfer level description of the network application into a bitstream definition comprises to optimize the register-transfer level description of the network application.

6. The computing device of claim 1 , wherein to compile the register-transfer level description of the network application into the bitstream definition comprises to optimize the plurality of TCAM-SRAM structures to generate corresponding logic gates.

7. The computing device of claim 1 , wherein:
to analyze the network application source program comprises to determine a control flow of the network application, wherein the control flow is indicative of an order of match-action tables; and
to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate multiplexer logic based on the control flow.

8. The computing device of claim 1 , wherein:
to analyze the network application source program comprises to determine a control flow of the network application, wherein the control flow is indicative of an order of match-action tables; and
to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate congestion management logic based on the control flow.

9. The computing device of claim 1 , wherein:
to analyze the network application source program comprises to analyze a definition of a match-action table; and
to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate a lookup block to access the match-action table in an external memory.

10. The computing device of claim 9 , wherein to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate a modify block to apply one or more actions from the match-action table to a network packet.

11. The computing device of claim 1 , wherein the computing device further comprises a network interface controller, and wherein the network interface controller comprises the field-programmable gate array.

12. One or more non-transitory, machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a computing device to:
analyze a network application source program, wherein the network application source program comprises a declarative description of a network application in a domain-specific language, wherein to analyze the network application source program comprises to generate a parse graph that includes a plurality of nodes based on the network application source program;
translate the declarative description of the network application into a register-transfer level description of the network application, wherein to translate the declarative description of the network application into the register-transfer level description of the network application comprises to generate a plurality of TCAM-SRAM structures, wherein each TCAM-SRAM structure corresponds to a node of the parse graph; and
compile the register-transfer level description of the network application into a bitstream definition of the network application, wherein the bitstream is targeted to a field-programmable gate array, wherein to compile the register-transfer level description of the network application into the bitstream definition comprises to optimize a first TCAM-SRAM structure of the plurality of TCAM-SRAM structures by replacing the first TCAM-SRAM structure with a state machine comparison logic.

13. The one or more non-transitory, machine-readable storage media of claim 12 , wherein the plurality of instructions, when executed, further cause the computing device to program the field-programmable gate array with the bitstream definition in response to compiling the register-transfer level description.

14. The one or more non-transitory, machine-readable storage media of claim 12 , wherein the plurality of instructions, when executed, further cause the computing device to partially reconfigure the field-programmable gate array with the bitstream definition in response to compiling the register-transfer level description.

15. The one or more non-transitory, machine-readable storage media of claim 14 , wherein the plurality of instructions, when executed, further cause the computing device to:
switch from an active block of the field-programmable gate array to a backup block of the field-programmable gate array in response to partially reconfiguring the field-programmable gate array;
wherein to partially reconfigure the field-programmable gate array comprises to program the backup block with the bitstream definition.

16. The one or more non-transitory, machine-readable storage media of claim 12 , wherein to compile the register-transfer level descri

Assignees

• Intel Corp

Inventors

• Daly Daniel P
• Willis Thomas E
• Wang Pat
• Anand Vishal
• Nguyen Hung
• Apte Varsha

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G11C15/04

  using semiconductor elements · CPC title

• G06F8/51 Primary

  Source to source · CPC title

• G06F8/41

  Compilation · CPC title

• G06F8/443

  Optimisation · CPC title