Method for configuring bandwidth for supporting broadband carrier in communication system
US-2024421968-A1 · Dec 19, 2024 · US
US10264540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10264540-B2 |
| Application number | US-201715726011-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 5, 2017 |
| Priority date | Oct 7, 2016 |
| Publication date | Apr 16, 2019 |
| Grant date | Apr 16, 2019 |
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A near field communication (NFC) device configured to use in preparing a carrier signal for active load modulation supporting both synchronous and asynchronous transmissions. The NFC device comprises a local clock generator for generating a reference clock signal (REF_CLK), a clock extractor for recovering a clock signal (EXT_CLK) generated by an NFC initiator device, a frequency tracking module (FTM) for performing a frequency tracking operation based on an input clock signal (REF_CLK or EXT_CLK) to produce a FTM output with its frequency aligned with the input clock signal, and a phase tracking module (PTM) for performing a phase tracking operation on the FTM output based on EXT_CLK to produce a PTM output with its phase aligned with EXT_CLK.
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What is claimed is: 1. A near field communication (NFC) device for use in preparing a carrier signal for active load modulation transmission, the NFC device comprising: a local clock generator configured to generate a reference clock signal; a clock extractor configured to recover a clock signal generated by an NFC initiator device; a frequency tracking module (FTM) configured to perform a frequency tracking operation based on an input clock signal to produce a FTM output with its frequency aligned with the input clock signal wherein the input clock signal is the reference clock signal or the recovered clock signal, wherein the FTM is an analog phase-locked loop (PLL) system, comprising: a phase-frequency detector (PFD) configured to receive the input clock signal and a feedback signal from a frequency divider (FD), compare phase and/or frequency of the feedback signal with the input clock signal, and produce a control signal in response to an offset in phase and/or frequency between the feedback signal and the input clock signal; a loop filter (LF) configured to receive the control signal from the PFD, perform a filtering operation on the control signal, and produce a control value associated to the offset in phase and/or frequency between the feedback signal and the input clock signal; a voltage controlled oscillator (VCO) configured to receive the control value from the LF and produce a VCO output with its phase and/or frequency adjusted based on the control value wherein the VCO output is served as the FTM output; and the FD is configured to receive the VCO output from the VCO, divide frequency of the VCO output by a number which is changeable to any suitable value to alter frequency of the VCO output to be equal or closer to frequency of the input clock signal, and produce a feedback signal to be fed into the PFD; wherein the feedback signal is aligned with the input clock signal when the feedback signal and the input clock signal are in-phase and their frequencies are equal or close to each other within an acceptable frequency accuracy; and a phase tracker configured to perform a phase tracking operation on the FTM output based on the recovered clock signal to produce a phase tracker output with its phase aligned with the recovered clock signal; wherein the phase tracker output at a desired frequency and phase is served as the carrier signal for use in load modulating data of the NFC device to form a load modulated signal to be actively transmitted to the NFC initiator device. 2. The NFC device of claim 1 , wherein the FTM further comprising: a multiplexer configured to select the input clock signal which is either the reference clock signal from the local clock generator or the recovered clock signal from the clock extractor. 3. The NFC device of claim 1 , wherein the input clock signal is the reference clock signal which is independent of the clock signal generated by the initiator device, the PLL system of the FTM is able to operate continuously in a closed loop even during active load modulation transmission. 4. The NFC device of claim 1 , wherein the input clock signal is the recovered clock signal which is dependent on the clock signal generated by the initiator device, the PLL system of the FTM is required to convert to an open loop during active load modulation transmission. 5. The NFC device of claim 1 , wherein the local clock generator is a temperature-compensated crystal oscillator. 6. The NFC device of claim 1 , wherein the phase tracker comprises: a phase interpolator, a phase sampler, and a digital loop filter (DLF) connected sequentially to form a feedback loop system to perform the phase tracking operation to track a desired clock phase based on the recovered clock signal; wherein the phase sampler comprises a circuitry configured to receive the recovered clock signal and a phase interpolation (PI) output from the phase interpolator, compare phase of the recovered clock signal with the PI output, and produce a digital signal in response to a phase offset between the recovered clock signal and the PI output; wherein the DLF comprises a circuitry configured to receive the digital signal from the phase sampler, perform a filtering operation on the digital signal, and produce a digital control signal associated to the phase offset between the recovered clock signal and the PI output; wherein the phase interpolator comprises a circuitry configured to receive a first plurality of FTM outputs with equally spaced phases by a first phase difference from the FTM, interpolate the first plurality of FTM outputs to form a second plurality of FTM outputs with equally spaced phases by a second phase difference wherein the second plurality of FTM outputs is greater than the first plurality of FTM outputs, and select one of the second plurality of FTM outputs to be output from the phase interpolator as an PI output based on the digital control signal received from the DLF such that the PI output has the closest phase to the recovered clock signal among the second plurality of FTM outputs wherein the PI output is served as the phase tracker output and fed into the phase sampler; wherein the PI output is aligned with the recovered clock signal when the PI output and the recovered clock signal are in-phase or close to each other within an acceptable phase accuracy. 7. The NFC device of claim 1 , wherein the phase tracker comprises: a phase interpolator, a time-to-digital converter (TDC), and a phase selector connected to form a system to perform the phase tracking operation to track a desired clock phase based on the recovered clock signal; wherein the phase interpolator comprises a circuitry configured to receive a first plurality of FTM outputs with equally spaced phases by a first phase difference from the FTM, interpolate the first plurality of FTM outputs to form a second plurality of FTM outputs with equally spaced phases by a second phase difference wherein the second plurality of FTM outputs is greater than the first plurality of FTM outputs, and send the second plurality of FTM outputs to the TDC and the phase selector concurrently; wherein the TDC comprises a circuitry configured to receive the recovered clock signal and the second plurality of FTM outputs from the phase interpolator, compare phase of the recovered clock signal with the second plurality of FTM outputs, and produce a digital control signal associated to phase relationship between the recovered clock signal and the second plurality of FTM outputs; wherein the phase selector configured to receive the digital control signal from the TDC and the second plurality of FTM outputs from the phase interpolator, and select one of the second plurality of FTM outputs to be output from the phase selector as a phase selection (PS) output based on the digital control signal such that the PS output has the closest phase to the recovered clock signal among the second plurality of FTM outputs wherein the PS output is served as the phase tracker output; wherein the PS output is aligned with the recovered clock signal when the PS output and the recovered clock signal are in-phase or close to each other within an acceptable phase accuracy. 8. The NFC device of claim 6 , wherein the feedback loop system of the phase tracker is converted to an open loop during active load modulation transmission. 9. A method for preparing a carrier signal for active load modulation transmission by a near field communication (NFC) device, the method comprising: generating a reference clock signal by a local clock generator in the NFC device; recovering a clock signal generated by an NFC initiator device by a clock extractor in the NFC device; performing a frequency tracking operatio
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