Random sampling for horizontal noise reduction

Patent metadata

Field	Value
Publication number	US-10264200-B2
Application number	US-201615390292-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Dec 23, 2016
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

An example apparatus for random sampling for horizontal noise reduction includes readout circuitry coupled to receive image data from an array of pixels, the readout circuitry including a plurality of sample and hold (S&H) circuits coupled to respective ones of a plurality of bitlines to sample and hold the image data in response to a plurality of S&H control signals, each of the plurality of S&H circuits including an S&H capacitor and an S&H switch. The S&H capacitor samples and holds respective image data, and the S&H switch coupled between a respective bitline and the respective S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals to open/close the S&H switch, where each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different time.

First claim

What is claimed is:

1. An apparatus comprising:
readout circuitry coupled to receive image data from an array of pixels via a plurality of bitlines, the readout circuitry including a plurality of sample and hold (S&H) circuits coupled to respective ones of the plurality of bitlines to sample and hold the image data in response to a plurality of S&H control signals provided by control circuitry, each of the plurality of S&H circuits including:
an S&H capacitor coupled to sample and hold respective image data; and
an S&H switch having one side coupled to a respective bitline of the plurality of bitlines and having an opposite side coupled to the S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals provided by the control circuitry to open and close the S&H switch,

wherein each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different randomized time in response to a respective one of the S&H control signals provided by the control circuitry,
wherein each of the plurality of S&H switches are hardwired to an S&H control line of a plurality of S&H control lines in a random pattern.

2. The apparatus of claim 1 , wherein the plurality of S&H control lines is less than the plurality of bitlines.

3. The apparatus of claim 2 , wherein the random pattern the plurality of S&H control lines is coupled to a respective number of S&H control switches repeats for the plurality of bitlines.

4. The apparatus of claim 1 , wherein each of the plurality of S&H control signals includes a minimum hold time and a random additional hold time, and wherein the random additional hold time is different for each of the plurality of S&H control signals.

5. An imaging system, comprising:
a pixel array including a plurality of pixels arranged in rows and columns, and further including a plurality of bitlines, with each of the plurality of bitlines associated with one of the columns, wherein each pixel of the pixel array photogenerates image data in response to image light;
control circuitry coupled to provide a plurality of sample and hold (S&H) control signals;
readout circuitry coupled to the plurality of bitlines, wherein the readout circuitry is coupled to receive the image data from the pixel array and perform analog-to-digital conversion of the image data, wherein the readout circuitry is coupled to sample and hold (S&H) the image data, and wherein the readout circuitry includes a plurality of S&H circuits coupled to the plurality of bitlines and coupled to receive the plurality of S&H control signals provided by the control circuitry, each of the plurality of S&H circuits comprising:
an S&H capacitor coupled to sample and hold respective image data; and
an S&H switch having one side coupled to a respective bitline of the plurality of bitlines and having an opposite side coupled to the S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals provided by the control circuitry to open and close the S&H switch,

wherein each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different randomized time in response to a respective one of the S&H control signals provided by the control circuitry,
wherein each of the plurality of S&H switches are hardwired to an S&H control line of a plurality of S&H control lines in a random pattern.

6. The imaging system of claim 5 , wherein each of the plurality of S&H control signals includes a minimum hold time and a random additional hold time, and wherein the random additional hold time is different for each of the plurality of S&H control signals.

7. The imaging system of claim 5 , wherein each one of the plurality of S&H circuits is coupled to one of the plurality of S&H control lines, the plurality of S&H control lines coupled to deliver the plurality of S&H control signals.

8. The imaging system of claim 5 , wherein the plurality of S&H control lines is less than the plurality of bitlines, and wherein the plurality of S&H control lines is coupled to a respective number of bitlines of the plurality of bitlines.

9. The imaging system of claim 8 , wherein the plurality of S&H control lines is coupled to a respective number of bitlines of the plurality of bitlines in a random pattern.

10. The imaging system of claim 9 , wherein the random pattern repeats for the plurality of bitlines.

11. The imaging system of claim 5 , wherein the readout circuitry further comprises an analog-to-digital converter coupled to receive the image data from the plurality of S&H circuits.

12. A method to randomly sample pixel voltage across a row of pixels, the method comprising:
transferring reference image data from each pixel of a row of pixels to a respective bitline of a plurality of bitlines;
simultaneously coupling the plurality of bitlines to a respective sample and hold (S&H) capacitor of a plurality of S&H capacitors in response to a plurality of S&H control signals provided by control circuitry to charge the S&H capacitor with the reference image data from a respective pixel of the row of pixels; and
decoupling each of the plurality of S&H capacitors from the respective bitline of the plurality of bitlines at different randomized times in response to the plurality of S&H control signals provided by the control circuitry.

13. The method of claim 12 , wherein each S&H control signal of the plurality of S&H control signals simultaneously transitions to a high logic level to simultaneously couple the plurality of bitlines to a respective S&H capacitor, and wherein each S&H control signal of the plurality of S&H control signals transitions to a low logic level at the different randomized time to decouple each of the plurality of S&H capacitors from their respective bitline.

14. The method of claim 12 , wherein simultaneously coupling the plurality of bitlines to a respective S&H capacitor of a plurality of S&H capacitors in response to a plurality of S&H control signals comprises:
providing the plurality of S&H control signals to a plurality of S&H switches to cause each of the plurality of S&H switches to simultaneously close, wherein causing each of the plurality of S&H switches couples the plurality of bitlines to their respective S&H capacitors.

15. The method of claim 12 , wherein decoupling each of the plurality of S&H capacitors from the respective bitline of the plurality of bitlines at different randomized times in response to the plurality of S&H control signals comprises:
providing the plurality of S&H control signals to a plurality of S&H switches to cause each of the plurality of S&H switches to open at the different randomized times, wherein causing each of the plurality of S&H switches decouples the plurality of bitlines from their respective S&H capacitors.

16. The method of claim 12 , wherein each S&H control signal of the plurality of control signals has a minimum hold time at a high logic level and the different randomized time before transitioning to a low logic level, wherein a transition to the high logic level occurs at a same time for each of the plurality of S&H control signals, and wherein the different randomized time before transitioning low is different for each S&H control signal of the plurality of S&H control signals.

Assignees

• Omnivision Tech Inc

Inventors

• Johansson Robert

Classifications

• H04N25/677 Primary

  for reducing the column or line fixed pattern noise · CPC title

• H04N5/378 Primary

  Electricity · mapped topic

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/618 Primary

  for random or high-frequency noise · CPC title